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STW81102ATR 数据表(PDF) 31 Page - STMicroelectronics |
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STW81102ATR 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 43 page ![]() STW81102 SPI digital interface 31/43 6.2 Timing specification Figure 27. SPI Timing specification Table 18. SPI data structure MSB LSB Address Data for Register (24 bits) A1 A0 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 19. Address decoder and outputs Address Outputs A1 A0 DATABITS D23-D0 No Name Function 00 24 0 ST1 Reference divider, VCO amplitude, VCO Calibration, Charge Pump current, Prescaler Modulus 0 1 24 1 ST2 Functional modes, VCO dividers 1 0 24 2 ST3 Reserved 1 1 24 3 ST4 Reserved Table 20. SPI Timing specification Parameter Description Min. Typ. Max. Unit tsetup DATA to CLOCK setup time 0.8 ns thold DATA to clock hold time 0.2 ns tclk CLOCK cycle period 10 ns tload LOAD pulse width 3 ns tclk_loadr CLOCK to LOAD rising edge 2 ns tclk_loadf CLOCK to LOAD falling edge 0.5 ns |
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