| 数据搜索系统,热门电子元器件搜索 |
|
LTC4253IGN 数据表(PDF) 25 Page - Linear Technology |
|
|
|||||||||||||||||||||||||||||
LTC4253IGN 数据表(HTML) 25 Page - Linear Technology |
|
25 / 32 page ![]() LTC4253 25 4253f APPLICATIO S I FOR ATIO (Refer to Block Diagram) Figure 10. Undervoltage Timing (All Waveforms are Referenced to VEE) 50 µA VSQTMRL UV CLEARS VUVHI, CHECK OV CONDITION, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 • VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS UV TIMER GATE SENSE SS DRAIN PWRGD1 PWRGD2 PWRGD3 SQTIMER EN2 EN3 12 3 4 56 7 8 9 A B C D 4253 F10 INITIAL TIMING GATE START-UP 20 • (VACL + VOS) 20 • (VCB + VOS) 20 • VOS 5 µA 5 µA UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES VUVLO VGATEL VUVHI VACL VSQTMRH VSQTMRL VCB 5 µA 5 µA 50 µA VSQTMRH VDRNCL VDRNL VIN – VGATEH 50 µA 200 µA + 8 • IDRN VTMRH VTMRL 5 µA Circuit Breaker Timing In Figure 13a, the TIMER capacitor charges at 200 µA if the SENSE pin exceeds VCB but VDRN is less than 6.15V. If the SENSE pin returns below VCB before TIMER reaches the VTMRH threshold, TIMER is discharged by 5µA. In Figure 13b, when TIMER exceeds VTMRH, GATE pulls down immediately and the chip shuts down. In Figure 13c, multiple momentary faults cause the TIMER capacitor to integrate and reach VTMRH followed by GATE pull down and the chip shuts down. During chip shutdown, LTC4253 latches TIMER high with a 5 µA pull-up current source. Resetting a Fault Latch A latched circuit breaker fault of the LTC4253 has the benefit of a long cooling time. The latched fault can be reset by pulsing the RESET pin high until the TIMER pin is pulled below VTMRL( 1V ) as shown in Figure 14. After the RESET pulse, SS and GATE ramp up without an initial timing cycle provided the interlock conditions are satis- fied. Alternative methods of reset include using an external switch to pulse the UV pin below VUVLO or the VIN pin below (VLKO – VLKH). Pulling the TIMER pin below VTMRL and the SS pin to 0V then simultaneously releasing them also achieves a reset. An initial timing cycle is generated |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |