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LTC4253IGN 数据表(PDF) 27 Page - Linear Technology

部件名 LTC4253IGN
功能描述  -48V Hot Swap Controller with Sequencer
PDF  32 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC4253IGN 数据表(HTML) 27 Page - Linear Technology

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LTC4253
27
4253f
APPLICATIO S I FOR ATIO
(Refer to Block Diagram)
tion, Interlock Conditions section. If not, the GATE pin will
ramp up in a soft start cycle without going through an
initial cycle.
Analog Current Limit and Fast Current Limit
In Figure 15a, when SENSE exceeds VACL, GATE is regu-
lated by the analog current limit amplifier loop. When
SENSE drops below VACL, GATE is allowed to pull up. In
Figure 15b, when a severe fault occurs, SENSE exceeds
VFCL and GATE immediately pulls down until the analog
current amplifier establishes control. If the severe fault
causes VOUT to exceed VDRNCL, the DRAIN pin is clamped
at VDRNCL. IDRN flows into the DRAIN pin and is multiplied
by 8. This extra current is added to the TIMER pull-up
current of 200
µA. This accelerated TIMER current of
(200
µA + 8 • IDRN)producesashortercircuitbreakerfault
VACL
VCB
VIN – VGATEH
OV
TIMER
GATE
SENSE
SS
12 34
5
6 7 8 9
GATE
START-UP
4253 F12
OV DROPS BELOW VOVLO, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 • VOS
OV OVERSHOOTS VOVHI. GATE AND SS ARE PULLED DOWN, PWRGD SIGNALS AND TIMER ARE UNAFFECTED
VOVHI
VOVLO
VTMRH
VGATEL
20 • (VACL + VOS)
20 • (VCB + VOS)
20 • VOS
5
µA
50
µA
50
µA
5
µA
200
µA + 8 • IDRN
CB FAULT
CB FAULT
CB FAULT
CB FAULT
12
1
2
1
2
3
4
TIMER
GATE
SENSE
VOUT
SS
DRAIN
PWRGD1
TIMER
GATE
SENSE
VOUT
SS
DRAIN
PWRGD1
TIMER
GATE
SENSE
VOUT
SS
DRAIN
PWRGD1
4253 F13
CB TIMES-OUT
CB TIMES-OUT
VTMRH
VACL
VCB
VACL
VCB
5
µA
5
µA
VDRNCL
200
µA + 8 • IDRN
200
µA + 8 • IDRN
VTMRH
VACL
VCB
VDRNCL
200
µA + 8 • IDRN
VTMRH
Figure 12. Overvoltage Timing (All Waveforms are Referenced to VEE)
Figure 13. Circuit Breaker Timing Behavior (All Waveforms are Referenced to VEE)
(13a) Momentary Circuit Breaker Fault
(13b) Circuit Breaker Time-Out
(13c) Multiple Circuit Breaker Fault



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