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ISO808 数据表(PDF) 12 Page - STMicroelectronics |
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ISO808 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 38 page ![]() Table 8. Logic inputs and output Symbol Parameter Test conditions Min. Typ. Max. Unit VIL LOAD, SYNC, INX and OUT_EN low level voltage -0.3 0.3 x VDD V VIH LOAD, SYNC, INX and OUT_EN high level voltage 0.7 x VDD VDD +0.3 V VI(HYST) LOAD, SYNC, INX and OUT_EN hysteresis voltage VDD = 5 V 100 mV IIN LOAD, SYNC, INX and OUT_EN current VIN = 5 V 10 55 90 μA Table 9. Parallel interface timings (VDD = 5 V; VCC = 24 V; -40 °C < TJ < 125 °C) Symbol Parameter Test conditions Min. Typ. Max. Unit tdis(SYNC) SYNC disable time Sync. control mode 10 μs tdis(DCM) SYNC, LOAD disable time Direct control mode 80 ns tw(SYNC) SYNC negative pulse width Sync. control mode 20 195 μs tsu(LOAD) LOAD setup time Sync. control mode 80 ns th(LOAD) LOAD hold time Sync. control mode 400 ns tw(LOAD) LOAD pulse width Sync. control mode 240 ns tsu(IN) Input setup time 80 ns th(IN) Input hold time 10 ns tw(IN) Input pulse width Sync. control mode 160 ns Direct control mode 20 μs tINLD IN to LOAD time Direct control mode from IN variation to LOAD falling edge 80 ns tLDIN LOAD to IN time Direct control mode from LOAD falling edge to IN variation 400 ns tjitter(SCM) Jitter on single channel Sync. control mode 6 μs tjitter(DCM) Direct control mode 20 Table 10. Internal communication timings (VDD = 5 V; VCC = 24 V; -40 °C < TJ < 125 °C) Symbol Parameter Test condition Min. Typ. Max. Unit frefresh Refresh delay 15 kHz tWD Watchdog time 272 320 400 μs ISO808, ISO808-1 Electrical characteristics DS14169 - Rev 1 page 12/38 |
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