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ADL6337ACRZB-R7 数据表(PDF) 22 Page - Analog Devices |
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ADL6337ACRZB-R7 数据表(HTML) 22 Page - Analog Devices |
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22 / 41 page  Data Sheet ADL6337 LINEARITY AND PERFORMANCE OPTIMIZATION (REFERENCE ONLY) analog.com Rev. B | 22 of 41 The ADL6337 includes a linearity and performance optimization feature to change two types of bias current blocks: IREF and IP3. The IREF adjustment feature is used for optimizing the output power and current consumptions. It can be individually tuned for each attenuation state (0, 1, 2, and 3) and for AMP1 and AMP2, which are controlled via ATTSEL1 and ATTSEL2. The enable and disable functions are controlled in Register 0x100[1:0] (seeTable 9), which are the main enable bits for AMP1 and AMP2. Table 11 shows a summary of IREF register address and bit names. Use the IP3 feature to tune linearity performance. It can be enabled and disabled individually for AMP1 and AMP2 and for each attenu- ation state (0, 1, 2, and 3). See Table 12. All attenuation states, however, use the same optimized values for AMP1 and AMP2. Store the optimized values in Register 0x105[4:0] for AMP1 (see Table 13) and Register 0x106[4:0] for AMP2 (see Table 14). The Typical Performance Characteristics section uses the specific IREF and IP3 values to achieve the performance shown in Table 15. Table 11. IREF Register Summary Attenuation State ATTSEL2 Pin 10 ATTSEL1 Pin 9 AMP1 AMP2 Register Address Bit Name Register Address Bit Name IREF 0 0 0 0x104[3:0] TRM_AMP1_IREF_0_0 0x104[7:4] TRM_AMP2_IREF_0_0 1 0 1 0x111[3:0] TRM_AMP1_IREF_1 0x111[7:4] TRM_AMP2_IREF_1 2 1 0 0x112[3:0] TRM_AMP1_IREF_2 0x112[7:4] TRM_AMP2_IREF_2 3 1 1 0x113[3:0] TRM_AMP1_IREF_3 0x113[7:4] TRM_AMP2_IREF_3 Table 12. IP3 Enable/Disable Register Bits Attenuation State ATTSEL2 Pin 10 ATTSEL1 Pin 9 AMP1 AMP1 Register Address Bit Name Register Address Bit Name 0 0 0 0x100 [5] AMP1_IP3_OFF_0_0 0x100 [6] AMP2_IP3_OFF_0_0 1 0 1 0x110 [0] AMP1_IP3_OFF_1 0x110 [4] AMP2_IP3_OFF_1 2 1 0 0x110 [1] AMP1_IP3_OFF_2 0x110 [5] AMP2_IP3_OFF_2 3 1 1 0x110 [2] AMP1_IP3_OFF_3 0x110 [6] AMP2_IP3_OFF_3 Table 13. 0x105 IP3 Register for AMP1 Bits Bit Name Description Reset Access [7:5] RESERVED Reserved. 0x0 R [4:0] TRM_AMP1_IP3_0 Amp 1 IP3 Trim When TXENP = 1. 0x0 R/W Table 14. 0x106 IP3 Register for AMP2 Bits Bit Name Description Reset Access [7:5] RESERVED Reserved. 0x0 R [4:0] TRM_AMP2_IP3_0 Amp 2 IP3 Trim When TXENP = 1. 0x5 R/W Table 15. Optimized IREF and IP3 Values Variant Operating Frequency (MHz) TRM_AMP1_IP3_0 TRM_AMP2_IP3_0 TRM_AMP1_IREF_0_0, TRM_AMP1_IREF_1 TRM_AMP1_IREF_2 TRM_AMP1_IREF_3 TRM_AMP2_IREF_0_0 TRM_AMP2_IREF_1 TRM_AMP2_IREF_2 TRM_AMP2_IREF_3 ADL6337-A 500 to 1000 2 (0x2) 3 (0x3) 13 (0xD) 11 (0xB) ADL6337-B 1350 to 2800 5 (0x5) 5 (0x5) 12 (0xC) 11 (0xB) |
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