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ADL6337ACRZB-R7 数据表(PDF) 23 Page - Analog Devices

部件名 ADL6337ACRZB-R7
功能描述  35 dB Gain, 500 MHz to 5200 MHz Transmit VGA
PDF  41 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADL6337ACRZB-R7 数据表(HTML) 23 Page - Analog Devices

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Data Sheet
ADL6337
SPI
analog.com
Rev. B | 23 of 41
The SPI of the ADL6337 allows device configuration for specific
functions or operations via a 3- or 4-wire SPI mode. This interface
consists of four control lines: SCLK, SDIO, SDO, and CS for
4-wire SPI mode. SCLK, SDIO, and CS are used for 3-wire SPI
mode and the default setting is configured as 3-wire SPI mode. To
enable 4-wire SPI mode, set SDOACTIVE[3] and SDOACTIVE_[4]
in Register 0x000 to 1. The timing requirements for the 4-wire SPI
port are shown in Figure 4.
It is recommended to assert the software reset every time when
the power is ramped. There are two types of the software reset
implemented in the ADL6337 (see Table 16). The first type resets
only a specific chip to send 0x01 in Register 0x020 when multiple
ADL6337 devices are connected (single-chip reset mode). In this
case, only one device can be reset, and the reset is not asserted
to the other devices. Defining the specific SPI chip address in the
SPI transactions is also necessary. See the Configuring Multiple
Chips to Share the SPI Bus section. Another way is to reset multi-
ple ADL6337 devices simultaneously by sending 0x81 in Register
0x000 (broadcasting reset mode).
Table 16. Software Reset Type
Reset Type
Address
Data
Single-Chip Reset Mode
0x020
0x1
Broadcasting Reset Mode
0x000
0x81
The ADL6337 protocol consists of a read/write bit, six chip select
ID bits (3 MSBs are always 0s), nine register address bits, followed
by eight data bits. Both the address and data fields are organized
with the MSB first and end with the LSB by default. The chip select
ID bits are externally configured by the CS_A2, CS_A1, and CS_A0
pins.
The ADL6337 input logic level for the write cycle is with a 1.8 V
logic level.
On a read cycle, the SDO pin is configurable for 1.8 V (default) or
3.3 V output levels by setting the SPI_1P8_3P3_CTRL bit (Register
0x120, Bit 0).



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