LTC4331 datasheet(13/26 Pages) AD

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LTC4331

Rev 0

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APPLICATIONS INFORMATION

device, configured for local mode, encodes and transmits

the captured I2C events to the remote I2C network where

they are recreated on the remote I2C bus. If additional

LTC4331 devices configured as slaves, REMOTE set

low, are connected to the remote I2C network, they also

transmit the events to the 3rd tier I2C network, and so

on. The local side LTC4331 always holds SCL low on the

9th bit waiting for an (N)ACK response from the remote

slave device(s). When the local side LTC4331 receives the

response, SCL is released with the response data set on

the I2C bus. If the R/W bit is set to Write, the bus turns

around after the ACK and the local LTC4331 switches

back to slave-receive mode in order to capture the incom-

ing write data. After the 8th SCL clock, the bus and link

direction reverse in order to retrieve the (N)ACK response

from the remote slave device. This sequence continues

until the master sends a START or STOP condition. Data

to be transferred across the link is stored in a buffer if the

local I2C transaction is faster than the effective link rate.

See Figure10.

If a local LTC4331 detects that all remote slaves have

NACK’d the slave address byte, it ceases transmitting fur-

ther I2C data to the remote side until a STOP or REPEATED

START condition is detected. This feature prevents the

LTC4331 from stalling the bus unnecessarily when the

transaction is addressed to a separate local slave device.

Note that in this scenario, the remote side SCL is held low

until a STOP or START condition is detected. Unusually

long cycle times could activate the tTIMEOUT condition.

In the case of a read transaction to a remote slave device,

the local LTC4331 slave device stalls the bus during the

read data phase. During this time, the remote LTC4331

I2C master prefetches the next byte from the remote slave

device. The read data byte is transmitted across the dif-

ferential link and stored in a local buffer. As bits become

available in the local buffer, the local LTC4331 drives them

onto SDA and releases SCL according to the configured

setup time tSU:DAT:SLAVE. After the complete byte has been

read, the I2C bus and differential link are turned around.

The local I2C master either ACKs or NACKs during this

time. If the master ACKs, the sequence is repeated. This

bus and link direction is reversed, and the next byte is

prefetched from the remote slave device. If the master

then NACKs, the bus and link do not reverse direction.

The master is then expected to send a STOP or START

event. See Figure11.

Differential Link

Internally,theLTC4331utilizesahighperformanceRS485

compliant transceiver to communicate over the link. The

A and B pins are fault protected to ±60V. In addition, the

transceiver operates over an extended common mode

range of ±15V making it suitable for noisy environments

or systems with ground potential differences. Data is

exchanged between the LTC4331 devices using a custom

packet which has a selectable baud rate based on the

configuration of the SPEED1 and SPEED2 pins. Selectable

baud rates over the cable allow balancing performance

with cable length specific to the application. Both sides

of the link must be set to the same speed configuration in

order to match the baud rates and allow communication.

The LTC4331 allows slew rate limiting over the differential

linkoutputstoreduceEMIinsensitiveapplications.Setting

the SLO pin low activates the slew rate limiting circuit.

Once in slew limiting mode, SPEED1 and SPEED2 pins

must only be configured for Speed Index 0 or 1. Setting

SPEED1/2 to a speed index of 2 or higher when SLO is low

results in link data corruption regardless of cable length.

The LTC4331 I2C slave device extension solution is point-

to-point only. Multidrop or multipoint configurations on

the differential link are not allowed.

±40kV ESD Protection

The LTC4331 features exceptionally robust ESD protec-

tion. The link interface pins (A, B) feature protection to

±40kV HBM with respect to GND, VCC (with a 4.7F capac-

itor to GND), A or B without latchup or damage, during all

modes of operation or while unpowered.

Level 4 IEC ESD and EFT Protection

The improved ESD protection of the LTC4331 provides a

high level of protection in the IEC ESD and EFT (Electrical

Fast Transient) tests. The IEC ESD stress exceeds that of

the HBM test in peak current, amplitude, and rise time,

while the EFT test provides a prolonged repetitive stress.

Combined with the HBM test, the IEC tests help ensure

that the LTC4331 is robust under a wide range of real

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