Philips Semiconductors

Product specification

74F393

Dual 4-bit binary ripple counter

2

1988 Nov 01

853–0295 94977

FEATURES

DESCRIPTION

Master Reset (MR) inputs to each counter. The two counters are

identified by the “a” and “b” suffixes in the pin configuration. The

operation of each half of the 74F393 is the same. The counters are

inputs. The counter outputs are internally connected to provide

Clock inputs to succeeding stages. The outputs of the ripple counter

do not change synchronously and should not be used for high speed

High asynchronous inputs; one for each 4-bit counter. A High level

in the MR input overrides the Clock and sets the outputs Low.

PIN CONFIGURATION

14

13

12

11

10

9

8

7

6

5

4

3

2

1

GND

Q1b

Q2b

Q3b

Q0b

CPb

MRb

CPa

MRa

Q3a

Q0a

Q1a

Q2a

SF00704

TYPE

TYPICAL SUPPLY CURRENT

(TOTAL)

74F393

125MHz

40mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

14-pin plastic DIP

N74F393N

SOT27-1

14-pin plastic SO

N74F393D

SOT108-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

Clock inputs

1.0/1.0

20

µA/0.6mA

Master Reset inputs

1.0/1.0

20

µA/0.6mA

Data outputs

50/33.3

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

13

1

34

5

6

11

10

9

8

Q0a

Q1a

Q2a

Q3a

Q0b Q1b Q2b

Q3b

12

2

SF00705

VCC = Pin 14

GND = Pin 7

IEC/IEEE SYMBOL (IEEE/IEC)

SF00706

CTR DIV 16

2

1

12

13

3

4

5

6

11

10

9

8

CT=0

+

0

3

0

3

CTR DIV 16

CT=0

+