Rev. 1.1 January 2022

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AOZ9511QV

ALPHA & OMEGA

SEMIC ONDUCT OR

Detailed Description

The AOZ9511QV is an integrated half-bridge gate driver

for motor drive applications. The device includes one

half-bridge gate driver, capable of driving high-side and

low-side N-channel MOSFETs. The AOZ9511QV provides

adjustable source/sink current of both high/low-side gate

drive output current which can optimize performances of EMI

and efficiency on different PCB layout and applications.

The AOZ9511QV provides adjustable gate drive sink and

source current control, by doing this control methodology, it’s

able to optimize EMI and driver losses to improve overall

efficiency performance.

Inaddition,theAOZ9511QVprovidesseveralfaultprotections,

such as UVLO, OTP and non-overlapping mechanism.

The AOZ9511QV is available in a 23-pin 4mm×4mm QFN

package.

Non-overlapping

For forbidding shoot-through, HIN or LIN is invalid when

HIN or LIN goes high state before other one. For example,

low-side gate state keeps low regardless of the state of LIN

when HIN is high at first, and vice versa.

Fault Protection

In order to protect power MOSFETs, over temperature

protection (OTP) is implemented. AOZ9511QV will be

shutdown when OTP is occurred until VCC is reset. The

threshold of OTP is 140°C.

Adjustable Source/Sink Current

It’s hard to meet all of EMI specifications in different

applications. So, AOZ9511QV provides external adjustable

resistors for tuning gate drive source and sink current.

DVS is used to tune gate drive source and sink current,

respectively. A resistor connects between DVS pin and GND

to setting gate drive source/sink current by internal current

mirror, as illustrated Figure 13. Source and sink current use

maximum capability to drive when DVS pin is floating or the

voltage on DVS pin exceeds 4V. The suggestion range of

RDVS is 10kΩ~100kΩ.

DVS

1V

Sink

Source

1:2000:2000

DVS

DVS

R

V

I

1

=

RDVS

Figure 13. Source/Sink Current Setting

In addition, source and sink current controls are implemented

only during MOSFET Miller effect and VGS >1V, as illustrated

in Figure 14.

V

GS

I

HO/ILO

1V

Miller Effect

Setting by

DVS Pin

Figure 14. Source/Sink Current Implement Waveform