Rev. 1.1 January 2022

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Page 10 of 13

AOZ9511QV

ALPHA & OMEGA

SEMIC ONDUCT OR

Layout Considerations

Several layout tips are listed below for the best electric and

thermal performance.

1. The VIN pins and pad are connected to internal high

side switch drain. They are also low resistance thermal

conduction path. Connected a large copper plane to VIN

pins to help thermal dissipation.

2. Input capacitors should be connected to the VIN pins

and the PGND pins as close as possible to reduce the

switching spikes.

3. The VOUT pins and pad are connected to internal low

side switch drain. They are low resistance thermal

conduction path and most noisy switching node.

Connected a large copper plane to VOUT pins to help

thermal dissipation.

4. Decoupling capacitor CVCC should be connected to VCC

and AGND as close as possible.

5. Bootstrap capacitor CB should be connected to VB and

VOUT as close as possible.A ground plane is preferred.

PGND and AGND must be connected to the ground

plane through vias.

6. A ground plane is preferred. PGND and AGND must be

connected to the ground plane through vias

7. Keep sensitive signal traces such as feedback trace and

digital signals far away from the VOUT pins.

LIN

1

2

3

4

5

6

NC

DVS

NC

HIN

NC

16

15

13

12

VOUT

VOUT

VOUT

VIN

14

17

PGND

C

VCC

C

B

Figure 15. Layout Placement