Table 13. Truth table

Conditions

Logic input (VI)

Output

SD/OD

LIN

HIN

LVG

HVG

Shutdown enable half-bridge tri-state

L

X(1)

X(1)

L

L

Interlocking half-bridge tri-state

H

H

H

L

L

0 “logic state” half-bridge tri-state

H

L

L

L

L

1 “logic state” low-side direct driving

H

H

L

H

L

1 “logic state” high-side direct driving

H

L

H

L

H

1. X: do not care.

3.3

Waveform definitions

Figure 5. Dead time and interlocking waveform definitions

STIPN2M50-H

Waveform definitions

DS11935 - Rev 6

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