LIS2DUX12 datasheet(53/102 Pages) STMICROELECTRONICS

53 / 102 page

8.33

SELF_TEST (32h)

R/W

Table 86. SELF_TEST register

ST1

ST0

Table 87. SELF_TEST register description

ST[1:0]

These bits enable data acquisition during the self-test procedure.

8.34

I3C_IF_CTRL (33h)

R/W

Table 88. I3C_IF_CTRL register

DIS_

DRSTDAA

ASF_ON

BUS_ACT_

SEL_1

BUS_ACT_

SEL_0

Table 89. I3C_IF_CTRL register description

DIS_DRSTDAA

If 0, direct RSTDAA is supported.

If 1, direct RSTDAA is disabled.

ASF_ON

If 1, enables the anti-spike filter even if the dynamic address is assigned.

BUS_ACT_SEL_[1:0]

Bus available time selection for IBI (in-band interrupt):

(00: 20 μs;

01: 50 μs (default);

10: 1 ms;

11: 25 ms)

8.35

EMB_FUNC_STATUS_MAINPAGE (34h)

Table 90. EMB_FUNC_STATUS_MAINPAGE register

IS_FSM_LC

IS_SIGMOT

IS_TILT

IS_STEP_DET

Table 91. EMB_FUNC_STATUS_MAINPAGE register description

IS_FSM_LC

Interrupt status bit for FSM long counter timeout interrupt event. (1: interrupt detected; 0: no interrupt)

IS_SIGMOT

Interrupt status bit for significant motion detection. (1: interrupt detected; 0: no interrupt)

IS_TILT

Interrupt status bit for tilt detection. (1: interrupt detected; 0: no interrupt)

IS_STEP_DET

Interrupt status bit for step detection. (1: interrupt detected; 0: no interrupt)

LIS2DUX12

SELF_TEST (32h)

DS14071 - Rev 2

page 53/102

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