LIS2DUX12 datasheet(39/102 Pages) STMICROELECTRONICS

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8.7

CTRL4 (13h)

R/W

Table 30. CTRL4 register

INACT_

ODR1

INACT_

ODR0

BDU

EMB_FUNC

_EN

FIFO_EN

0(1)

SOC

BOOT

1. This bit must be set to 0 for the correct operation of the device.

Table 31. CTRL4 register description

INACT_ODR[1:0]

If the activity/inactivity function is enabled, then these bits select the accelerometer ODR during inactivity

status, see Table 32.

BDU

Sensing chain block data update

(0: output registers MSByte and LSByte independent continuous update (default);

1: output registers are not updated until MSByte and LSByte have both been read)

EMB_FUNC_EN

Enables embedded functions. To be set to 1 before configuring the embedded functions. Default value: 0

(0: disabled; 1: enabled)

FIFO_EN

Enables batching in FIFO. To be set to 1 before configuring the FIFO buffer. Default value: 0

(0: disabled; 1: enabled)

SOC

Start of conversion bit. When one-shot mode using the interface (ODR[3:0] = 1111 in the CTRL5 (14h)

BOOT

Reboots memory content. Default value: 0

(0: normal operating mode; 1: reboot memory content)

This bit is automatically cleared. For proper execution of the boot procedure, set the device in high-

performance mode.

Table 32. ODR frequency in inactivity state

INACT_ODR1 INACT_ODR0

Frequency [Hz]

Stationary/motion detection: when selected, no ODR change is done if inactivity condition is

detected (default)

1.6

LIS2DUX12

CTRL4 (13h)

DS14071 - Rev 2

page 39/102

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