Data Sheet

ADRF5534

3.1 GHz to 4.2 GHz, Receiver Front End

Rev. 0

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FEATURES

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Integrated RF front end

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LNA and high-power silicon SPDT switch

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On-chip bias and matching

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Single-supply operation

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Gain: 35.5 dB typical at 3.6 GHz

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Gain flatness: 1.5 dB at 25°C across 400 MHz bandwidth

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Low noise figure: 1.3 dB typical at 3.6 GHz

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Low insertion loss: 0.8 dB typical at 3.6 GHz

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High-power handling at TCASE = 105°C

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Full lifetime

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LTE average power (8 dB PAR): 37 dBm

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Single event (<10 sec operation)

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LTE average power (8 dB PAR): 39 dBm

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High Input IP3: −4 dBm

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Low-supply current

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Receive operation: 120 mA typical at 5 V

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Transmit operation: 15 mA typical at 5 V

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Positive logic control

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5 mm × 3 mm, 24-lead LFCSP package

APPLICATIONS

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Wireless infrastructure

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TDD massive multiple input and multiple output (MIMO) and

active antenna systems

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TDD-based communication systems

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The ADRF5534 is an integrated RF, front-end multichip module

designed for time division duplex (TDD) applications. The device

operates from 3.1 GHz to 4.2 GHz. The ADRF5534 is configured

with an LNA and a high-power, silicon, SPDT switch.

In the receive operation at 3.6 GHz, the LNA offers a low noise

figure (NF) of 1.3 dB and a high gain of 35.5 dB with a third order

input intercept point (IIP3) of −4 dBm.

In the transmit operation, the switch provides a low insertion loss

of 0.8 dB and handles a long-term evolution (LTE) average power

of 37 dBm for a full lifetime operation (8 dB peak to average ratio

(PAR)) and 39 dBm for a single event (<10 sec) LNA protection

operation.

The device is featured in an RoHS compliant, compact, 5 mm × 3

mm, 24-lead LFCSP package.