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M68AW511A 数据表(PDF) 4 Page - STMicroelectronics

部件名 M68AW511A
功能描述  4 Mbit (512K x8) 3.0V Asynchronous SRAM
PDF  21 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M68AW511A 数据表(HTML) 4 Page - STMicroelectronics

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M68AW511A
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SUMMARY DESCRIPTION
The M68AW511A is a 4 Mbit (4,194,304 bit)
CMOS SRAM, organized as 524,288 words by 8
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 2.7 to 3.6V supply.
This device has an automatic power-down feature,
reducing the power consumption by over 99%
when deselected.
The M68AW511A is available in two different
packages: 32-lead TSOP Type II and 32-lead SO.
Figure 2. Logic Diagram
Table 1. Signal Names
AI05445c
19
A0-A18
W
DQ0-DQ7
VCC
M68AW511A
G
VSS
8
E
A0-A18
Address Inputs
DQ0-DQ7
Data Input/Output
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground



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