L8150

General description

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4

General description

4.1

Drive stage

Voltage-controlled PWM drive.

Smooth drive architecture (see following dedicated paragraph).

External sense resistor as current limiter.

FR terminal: Low = Forward, High or Open = Backward.

4.2

Output

U, V, W upper and lower arm power transistors control output (6 outputs)

CMOS level (Low: 0V, High: 5V, need output buffer)

dead time (0, 1usec, 1.5usec selectable).

4.3

I/O

FG output: multiplexed by Hall signal (open drain)

(Hall signal after digital filter are used)

Forward/backward control

FAULT output: monitor signal for protection operation (low active, open drain), active if one

of over voltage, lower voltage, thermal protection, Hall sensor fail protection is operative

Torque optimizer: controlled by analog input

DM output is the monitor signal of Hall input sequence:

–

IF UVW hall signal sequence is as the direction set by FR, DM=H

–

IF UVW hall signal sequence is opposite for the direction set by FR, DM=L

–

Reset or some case in which UVW sequence can not be monitored, DM=H (Hall

signals after digital filter are used for this control).

4.4

Hall Sensor Input Terminals

There are 2 types of application, Hall device and Hall IC

Hall Device application: differential inputs with some bias

Hall IC application: one input is fixed around VREG/2 by resistor divider between VREG and

GND the other input comes from Hall IC whose span is between 0 and 5V.