Precharge and hall effects filtering time description

L8150

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for the successive TelMAX/6 and the behaviour is the one described in the startup sequence

with motor stopped.

6.2

Startup sequence with SD signal

●

Let's consider a startup sequence forced by SD, supposing the motor stopped:

Figure 18.

Startup sequence forced by SD, supposing the motor stopped

When the SD signal has a falling edge (corresponding to a VREG signal that's crossing the

lower voltage protection), the logic can produce a ZC signal, depending on FS signal

behaviour induced by Vsp voltage value. In any case, even if no ZC signal is produced, if the

motor is stopped and no Hall effect commutation is detected, the counter reaches its

saturation time TelMAX/6 and the system evolves like in the situation described in previous

startup sequence with motor stopped.

●

Let's consider a startup sequence forced by SD, supposing the motor rotating quickly in

the direction imposed by the FR signal:

Figure 19.

Startup sequence forced by SD, supposing the motor rotating quickly in

the direction imposed by the FR signal

SD

PRECHARGE

ZC

HALL BUS

FILTER

TIME

PHASES

PHASES EXCITED

400 us

400 us

400 us

T∆zc/576

T∆zc

Tel

U

TelMax/6

MOTOR ACCELERATING

400 us

400 us

SD

ZC

HALL BUS

FILTER TIME

PHASES

PHASES EXCITED

T∆zc/576

Tel

400 us

T∆zc/576

T∆zc/576

T∆zc/576

T∆zc

400 us