74HC_HCT4040_3

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

Product data sheet

Rev. 03 — 14 September 2005

15 of 24

Philips Semiconductors

74HC4040; 74HCT4040

12-stage binary ripple counter

[1]

∑(C

2

× f

13. Waveforms

propagation delay MR to Qn

see Figure 8

--68

ns

output transition time

see Figure 8

--22

ns

clock pulse width HIGH or LOW

see Figure 8

24

-

-

ns

master reset pulse width; HIGH

see Figure 8

24

-

-

ns

recovery time MR to CP

see Figure 8

15

-

-

ns

maximum operating frequency

see Figure 8

20

-

-

MHz

Table 10:

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Fig 8.

Clock (CP) to output (Qn) propagation delays, clock pulse width, output transition

times, maximum clock pulse frequency, master reset (MR) pulse width, master

reset to output (Qn) propagation delays and master reset to clock (CP) removal

time.

MR input

CP input

Q0 or Qn

output

001aad590