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M95640-DF 数据表(PDF) 39 Page - STMicroelectronics

部件名 M95640-DF
功能描述  64-Kbit serial SPI bus EEPROM with high-speed clock
PDF  53 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M95640-DF 数据表(HTML) 39 Page - STMicroelectronics

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DocID16877 Rev 19
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M95640-W M95640-R M95640-DF
DC and AC parameters
41
Table 19. AC characteristics (M95640-R, device grade 6)
Test conditions specified in Table 9 and Table 11
Symbol Alt.
Parameter
Previous
products(1)
New products(2)
Unit
VCC ≥ 1.8V
VCC ≥ 1.8V VCC ≥ 2.5V VCC ≥ 4.5V
Min.
Max. Min. Max. Min. Max. Min. Max.
fC
fSCK Clock frequency
-
2
-
5
-
10
-
20
MHz
tSLCH
tCSS1 S active setup time
150
-
60
-
30
-
15
-
ns
tSHCH tCSS2 S not active setup time
150
-
60
-
30
-
15
-
ns
tSHSL
tCS S deselect time
200
-
90
-
40
-
20
-
ns
tCHSH
tCSH S active hold time
150
-
60
-
30
-
15
-
ns
tCHSL
-S not active hold time
150
-
60
-
30
-
15
-
ns
tCH (3)
tCLH Clock high time
200
-
80
-
40
-
20
-
ns
tCL(3)
tCLL Clock low time
200
-
80
-
40
-
20
-
ns
tCLCH(4) tRC Clock rise time
-
2
-
2
-
2
-
2
µs
tCHCL(4)
tFC Clock fall time
-
2
-
2
-
2
-
2
µs
tDVCH
tDSU Data in setup time
50
-
20
-
10
-
5
-
ns
tCHDX
tDH Data in hold time
50
-
20
-
10
-
10
-
ns
tHHCH
-
Clock low hold time after HOLD
not active
150
-
60
-
30
-
15
-
ns
tHLCH
-
Clock low hold time after HOLD
active
150
-
60
-
30
-
15
-
ns
tCLHL
-
Clock low setup time before
HOLD active
0-
0
-
0
-
0
-
ns
tCLHH
-
Clock low setup time before
HOLD not active
0-
0
-
0
-
0
-
ns
tSHQZ(4) tDIS Output disable time
-
200
-
80
-
40
-
20
ns
tCLQV
tV
Clock low to output valid
-
200
-
80
-
40
-
20
ns
tCLQX
tHO Output hold time
0
-
0
-
0
-
0
-
ns
tQLQH(4) tRO Output rise time
-
200
-
80
-
20
-
10
ns
tQHQL(4) tFO Output fall time
-
200
-
80
-
20
-
10
ns
tHHQV
tLZ HOLD high to output valid
-
200
-
80
-
40
-
20
ns
tHLQZ(4)
tHZ HOLD low to output High-Z
-
200
-
80
-
40
-
20
ns
tW
tWC Write time
-
5
-
5
-
5
-
5
ms
1. For devices identified by process letter P.
2. For devices identified by process letter K.
3. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max).
4. Characterized only, not tested in production.



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