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©Copyright 2006. STATS ChipPAC Ltd. All rights reserved.

May 2006

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QFP-SD

Stacked Die Quad Flat Pack

SPECIFICATIONS

Die Thickness

100-600

µm (4-24mils)

Package Body Thickness

1.0, 1.4mm

Marking

Laser/ink

Packing Options

JEDEC tray/tape and reel

RELIABILITY

Moisture Sensitivity Level

JEDEC Level 3, 260°C reflow

Temperature Cycling

Condition C (-65°C to 150°C)

1000 cycles

High Temperature Storage

150°C, 1000 hrs

Pressure Cooker Test

121°C/100% RH/2 atm, 168 hrs

Temperature/Humidity Test

85°C/85% RH, 1000 hrs

PACKAGE CONFIGURATIONS

Package Size

Body Size (mm)

Lead Count

LQFP-SD

7 x 7 to 28 x 28

32 to 208

LQFP-ep-SD

10 x 10 to 24 x 24

64 to 216

TQFP-ep-SD

7 x 7 to 14 x 14

32 to 100

CROSS-SECTION

LQFP-SD

LQFP-ep-SD

TQFP-ep-SD

ELECTRICAL PERFORMANCE

Package

Pad Size

Lead/Wire

Resistance

Inductance

Capacitance

(mm)

(mm)

(mm)

(mOhm)

Self (nH)

Mutual (nH)

Self (pF)

Mutual (pF)

7 x 7 (32L)

138 x 138

1.4-2.2

11.0-18.0

0.64-0.99

0.31-0.49

0.21-0.33

0.07-0.12

2

120

1.65

0.45-0.85

0.1

0.01-0.02

14 x 14 (128L)

275 x 275

3.0-4.5

24.0-36.0

1.96-2.92

1.08-1.61

0.69-1.03

0.31-0.45

2

120

1.65

0.45-0.85

0.1

0.01-0.02

Note: Results are simulated values at 100MHz.

THERMAL PERFORMANCE

The thermal performance of each die in the stack is influenced by other die in the stack. Thermal performance is highly dependent on

package size, die size, substrate layers and thickness, and lead configuration. Simulation for specific applications should be performed.