VLS252012CX-1R5M datasheet(20/44 Pages) MICROCHIP

20 / 44 page

MCP16501

DS20006388A-page 20

 2020 Microchip Technology Inc.

LDO rail is started first (at time t1), by connecting

LEN to the VDDIO output (MCP16501D only).

• DDR supply/DDRIO voltage (VDDIODDR) is

started next after delay t2. From the MPU

perspective, t2 is not mandatory, but it facilitates

the use of an external 1.8V DC-DC or LDO for

LPDDR2/3 (VDDIODDR being the 1.2V supply of

the LPDDR2/3). This DC-DC can be initially

sequenced to VDDIO at start-up and maintained

on by VDDIODDR for Hibernate mode (backup

self-refresh).

• VDDCORE (and VDDCPU for other MPUs)

voltages are started last, after a delay of t3.

• Upon successful start-up of all the rails in the

power-up sequence, after delay t4, the Reset

signal (nRSTO) is deasserted and software

execution can start.

The start-up sequence can be initiated in two different

ways, also depending on the presence of a back-up

supply in the application:

nSTRT event (nSTRT pin pulled low),

maintained by PWRHLD assertion. In

applications with a backup battery, the PWRHLD

signal is typically already high before the nSTRT

event.

A low-to-high transition of the PWRHLD

signal, regardless of the nSTRT event. This is

only possible in applications with backup supply.

This mode is typically originated by an external

wake-up event asserted by a peripheral device

to the MPU Shutdown and Wake-up Controller

(SHDWC), which is still powered in Backup mode.

Delay t1 acts as a debouncing delay of the nSTRT

event. Therefore, nSTRT must be detected as low

continuously during t1 to validate the start-up event and

initiate the first sequence step. After the first sequence

step is started (at t1), nSTRT can be released to its high

level at any time. Also, subsequent high-low-high tog-

gling of nSTRT during the execution of the start-up

sequence, while visible at the nSTRTO output, will be

ignored by the sequencer and it will NOT reset the

start-up sequence under execution.

The following timing diagram in Figure 4-4 shows the

typical sequence for Case 1:

FIGURE 4-4:

Start-Up from nSTRT Timing

Diagram.

Note:

The nSTRT event needs the assertion of

PWRHLD to have the power-up sequence

completed successfully. If PWRHLD is not

yet high at the time nRSTO is to be

asserted, the MCP16501 automatically

initiates a turn-off sequence without any

positive glitches on nRSTO.

Where:

t1 = Delay from nSTRT falling to first output

VOUT1 starting (default 0.5 ms + device

wake-up time, about 100 µs)

t2 = Time from VOUT1 established to VOUT2

starting (default 8 ms)

t3 = Time from VOUT2 established to VOUT3

starting (default 4 ms)

t4 = Time from VOUT3 established to nRSTO

deassertion (default 16 ms)

t5 = Setup/hold times, min. 0 µs (internal

filtering applies)

VLS252012CX-1R5M 数据表(PDF) 20 Page - Microchip Technology

VLS252012CX-1R5M 数据表(HTML) 20 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载