HC05V7GRSSLASHD datasheet(134/170 Pages) NXP

134 / 170 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 120

MC68HC05V7 Specification Rev. 1.0

15.5.4.7

Invalid Active Bit

If the active to passive transition beginning the next data bit or symbol occurs between the

passive to active transition beginning the current data bit or symbol and

a, the current bit

would be invalid. See Figure 15-14(1).

15.5.4.8

Valid Active Logic One

If the active to passive transition beginning the next data bit or symbol occurs between

and

b, the current bit would be considered a logic one. See Figure 15-14(2).

15.5.4.9

Valid Active Logic Zero

If the active to passive transition beginning the next data bit or symbol occurs between

and

c, the current bit would be considered a logic zero. See Figure 15-14(3).

Figure 15-14 :

J1850 VPW Active Symbols

(1) Invalid Active

(2) Valid Active

(3) Valid Active

µs

128

µs

Bit

Logic One

Logic Zero

(4) Valid SOF

Symbol

200

µs

(5) Valid BREAK

Symbol

280

µs

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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