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HC05V7GRS/D 数据表(PDF) 167 Page - NXP Semiconductors |
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HC05V7GRS/D 数据表(HTML) 167 Page - NXP Semiconductors |
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167 / 170 page  SECTION 17: ELECTRICAL SPECIFICATIONS Page 153 MC68HC05V7 Specification Rev. 1.0 17.11.7 RECEIVER VPW SYMBOL TIMINGS (fMDLC = 1.048576 MHz, VBATT =12V, VCCA = 5.0V, VSSA2 = 0 V, TA = 25°C, unless otherwise noted) Note: The receiver symbol timing boundaries are subject to an uncertainty of ± 1 T MDLC µs due to sampling considerations. End of Data (EOD) 15 Ttvp3 198.0 200.0 202.0 µs End of Frame 16 Ttv4 278.0 280.0 282.0 µs Inter-Frame Separator (IFS) 17 Ttv6 298.0 300.0 302.0 µs Characteristic Number Symbol Min. Typ. Max. Unit Passive logic 0 10 Trvp1 34.0 64.0 96.0 µs Passive logic 1 11 Trvp2 96.0 128.0 163.0 µs Active logic 0 12 Trva1 96.0 128.0 163.0 µs Active logic 1 13 Trva2 34.0 64.0 96.0 µs Start of Frame (SOF) 14 Trva3 163.0 200.0 239.0 µs End of Data (EOD) 15 Trvp3 163.0 200.0 239.0 µs End of Frame 16 Trv4 239.0 280.0 320.0 µs Break 18 Trv7 239.0 800.0 — µs Characteristic Number Symbol Min. Typ. Max. Unit Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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