HC05V7GRSSLASHD datasheet(116/170 Pages) NXP

116 / 170 page

SECTION 15: MESSAGE DATA LINK CONTROLLER

Page 102

MC68HC05V7 Specification Rev. 1.0

The Rx Buffer will then be released back to the MDLC. If another message is available in

the second Rx Buffer at this time, the new message will then be made available to the CPU.

Following a write to the MRSR to release the Rx Buffer, this register should not be

accessed again until the RXMS bit is again verified to be set. This procedure will ensure

that the MRSR value does not change while it is being accessed by the CPU.

If, while performing the above operations, another message begins to arrive then the

second message will be placed in a duplicate Rx Buffer. The MDLC will always present the

oldest available message to the programmer, therefore only one Rx Buffer appears in the

memory map while the other one is filled with a newer message.

If both Rx Buffers are filled when a third new message arrives, the third message will be

ignored and the prior messages within the Rx Buffers will not be affected.

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HC05V7GRS/D 数据表(PDF) 116 Page - NXP Semiconductors