| 数据搜索系统,热门电子元器件搜索 |
|
STLC3075 数据表(PDF) 9 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STLC3075 数据表(HTML) 9 Page - STMicroelectronics |
|
9 / 26 page ![]() 9/26 STLC3075 3.2.4 Ringing When this mode is selected STLC3075 self generate an higher negative battery (-70V typ.) in order to allow a balanced ringing signal of typically 65Vpeak. In this condition both the DC and AC feedback loop are disabled and the SLIC line drivers operate as volt- age buffers. The ring waveform is obtained toggling the D2 control bit at the desired ring frequency. This bit in fact controls the line polarity (0=direct; 1= reverse). As in the ACTIVE mode the line voltage transition is performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see fig. 8). The shaping is defined by the CREV external capacitor. Figure 8. TIP/RING typical ringing waveform Selecting the proper capacitor value it is possible to get different crest factor values. The following table shows the crest factor values obtained with a 20Hz and 25Hz ring frequency and with 1REN. These value are valid either with European or USA specification: Table 9. (*) Distorsion already less than 10%. The ring trip detection is performed sensing the variation of the AC line impedance from on hook (relatively high) to off-hook (low). This particular ring trip method allows to operate without DC offset superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. It should be noted that such a method is optimised for operation on short loop applications and may not operate properly in presence of long loop applications (> 500 Ω). Once ring trip is detected, the DET output is activated (logic level low), at this point the card controller or a simple logic circuit should stop the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3075 in the proper operating mode (normally ACTIVE). 3.2.4.1 Ring Level in Presence of More Telephone in Parallel As already mentioned above the maximum current that can be drawn from the Vpos supply is controlled and limited via the external RSENSE. This will limit also the power available at the self generated negative battery. If for any reason the ringer load is too low the self generated battery will drop in order to keep the power CREV CREST FACTOR @20Hz CREST FACTOR @25Hz 22nF 1.2 1.26 27nF 1.25 1.32 33nF 1.33 Not significant (*) GND TIP RING dV/dT set by CREV 2.5V typ. 65V typ. VBAT 2.5V typ. |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |