STLC3075

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FUNCTIONAL DESCRIPTION

The STLC3075 is a device specifically developed for WLL VoIP and ISDN-TA applications.

It is based on a SLIC core, on purpose optimised for these applications, with the addition of a DC/DC con-

verter controller to fulfil the WLL and ISDN-TA design requirements.

The SLIC performs the standard feeding, signalling and transmission functions.

It can be set in three different operating modes via the D0, D1, D2 pins of the control logic interface (0 to

3.3V logic levels). The loop status is carried out on the DET pin (active low).

The DET pin is an open drain output to allow easy interfacing with both 3.3V and 5V logic levels.

The four possible SLIC’s operating modes are:

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CLK

Power Switch Controller Clock (typ. 125KHz). This pin can also be connected to CVCC or AGND.

When the CLK pin is connected to CVCC an internal auto-oscillation is internally generated and

it is used instead of the external clock. When the CLK pin is connected to AGND, the GATE

output is disabled.

24

GATE

Driver for external Power MOS transistor (P-chanell in Buck-boost configuration, N-channel in

Fly-back configuration).

25

RSENSE Voltage input for current sensing. RSENSE resistor should be connected close to this pin and

VPOS pin (Buck-boost) or GND (Fly-back). The PCB layout should minimize the extra resistance

introduced by the copper tracks.

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VPOS

Positive supply input.

27

CVCC

Internal positive voltage supply filter.

28

AGND

Analog Ground, must be shorted with BGND.

29

RLIM

Constant current feed programming pin (via RLIM). RLIM should be connected close to this pin

and AGND pin to avoid noise injection.

30

IREF

Internal bias current setting pin. RREF should be connected close to this pin and AGND pin to

avoid noise injection.

31

RTH

Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin and

AGND pin to avoid noise injection.

32

RD

DC feedback and ring trip input. RD should be connected close to this pin and AGND pin to avoid

noise injection.

33

ILTF

Transversal line current image output.

34

CSVR

Battery supply filter capacitor.

35

BGND

Battery Ground, must be shorted with AGND.

36

VBAT

Regulated battery voltage self generated by the device via DC/DC converter.

Must be shorted to VBAT1.

37

RING

2 wire port; RING wire (Ib is the current sunk into this pin).

41

TIP

2 wire port; TIP wire (Ia is the current sourced from this pin).

43

CREV

Reverse polarity transition time control. A proper capacitor connected between this pin and

AGND is setting the reverse polarity transition time. This is the same transition time used to

shape the "trapezoidal ringing" during ringing injection.

44

VBAT1

Frame connection. Must be shorted to VBAT.

Table 5. Pin Description (continued)

N°

Pin

Function