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Revision 2.2

2.0

Signal Definitions

This section defines the signals and describes the external

interface of the CS1301/CS1311 media companion. Figure

2-1 shows the signals organized by their functional groups.

The remaining subsections of this chapter describe:

• Section 2.1 "Ball Assignments": Provides a ball assign-

ment diagram and tables listing the signals sorted

according to ball number and alphabetically by signal

name.

• Section 2.2 "Signal Descriptions": Detailed descriptions

of each signal according to functional group.

• Section 2.3 "Reference Voltages": Discussion on ball

reference voltages.

2.1

BALL ASSIGNMENTS

The CS1301/CS1311 has a total of 169 functional pins,

digital power/ground. For pins with 5.0V input capability,

the VREF_PCI or VREF_PERIPH determines 3.3V or 5.0V

input tolerance. Unused pins can remain floating/uncon-

nected; all pins that drive a clock should drive a series

resistor.

Table 2-1 shows the types of I/O circuits used by the

CS1301/CS1311 series. Note that the # symbol in a signal

name indicates that the active or asserted state occurs

when the signal is at a low voltage level. Otherwise, the

signal is asserted when at a high voltage level.

Figure 2-1. Functional Block Diagram

Table 2-1. Ball Type Descriptions

Modes

Description

I

Input only, except during boundary scan.

O

Output only, except during boundary scan.

OD

Open Drain output, active pull low, no active

drive high, requires external pull-up.

I/O

Input or Output.

I/OD

Input with Open Drain output, active pull low,

no active drive high, requires external pull-up.

MM_DQ [ 31: 00]

MM_CLK [ 1:0]

MM_RAS#

MM_CAS#

MM_WE#

MM_DQM [ 3:0]

MM_CS[ 3:0] #

VREF_PCI

VREF_PERIPH

Video Out*

VO_CLK

Memory

Interface

Interface

TRI_TIMER_CLK

TRI_USERIRQ

System

Interface

Geode™

CS1301/CS1311

TRI_CLKIN

MM_A [13:00]

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG

VO_IO[2:1]

VO_DATA[07:00]

AO_OSCLK

AO_SCK

AO_WS

AO_SD[4:1]

SPDO

IIC-SDA

Audio Out

Interface

MM_CKE[1:0]

JTAG_TDO

IIC-SCL

TRI_RESET#

PCI_TRDY#

PCI_DEVSEL#

PCI_STOP#

PCI_AD [31: 00]

PCI_SERR#

PCI_CLK

PCI_GNT#

PCI_REQ#

PCI_IDSEL

PCI_FRAME#

PCI_IRDY#

PCI_INTD#

PCI_INTA#

PCI_INTB#

PCI_INTC#

PCI Bus

Interface

PCI_PAR

PCI_C/BE[3:0]#

PCI_PERR#

VI_CLK

VI_DVALID

VI_DATA[09:00]

Video In

*Video In and Audio In are supported by third party software solutions, not by the National Semiconductor solution.

Interface

AI_OSCLK

AI_SCK

AI_SD

AI_WS

Audio In*

Interface

S/PDIF

ACCESS.bus

BOOT_CLK

TESTMODE

SCANCPU

Test and

Measurement

Interface

Interface

Interface

(Total of 8) NC

Power, Ground

and No

Connections

Interface