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14

Revision 2.2

2.2.2

Memory Interface Signals

Signal Name

Ball

No.

Type

Description

MM_CLK0

Y10

O

SDRAM Output Clock (at 2x or 3x TRI_CLKIN frequency). Two identi-

cal outputs are provided to reliably drive several small memory configu-

rations without external glue. A series terminating resistor close to

CS1301/CS1311 is required to reduce ringing.

For driving a 50

Ω trace, a resistor of 27 to 33Ω is recommended. The

use of higher impedance traces in the SDRAM signals is not recom-

mended.

MM_CLK1

W10

MM_A[13:00]

See Table

2-3 on

page 12

O

Address Bus. Used for row and column addresses.

WARNING: Do not connect MM_A[13:11] directly to SDRAM A[13:11]

pins. Refer to Chapter 12 SDRAM Memory System of the Philips Semi-

conductor

PNX1300 Series Media Processors Data Book for accurate

connection diagrams.

MM_DQ[31:00]

See Table

2-3 on

page 12

I/O

32-Bit Data I/O Bus. The Main Memory Interface module also supports

a 16-bit I/O interface.

MM_CKE0

Y19

O

Clock Enable Output to SDRAMs. Two identical outputs are provided

in order to reliably drive several small memory configurations without

external glue.

MM_CKE1

U1

MM_CS0#

U2

O

Chip Select for DRAM rank n; active low. The chip select pins may be

used as address pins to support the 256-Mbit SDRAM device organized

in x16.

MM_CS1#

U20

MM_CS2#

U3

MM_CS3#

U19

MM_RAS#

W14

O

Row Address Strobe; active low.

MM_CAS#

Y15

O

Column Address Strobe; active low.

MM_WE#

W15

O

Write Enable; active low.

MM_DQM0

T19

O

Data Mask Enable. These are byte-enable signals for the 32-bit

MM_DQ bus.

MM_DQM1

R18

MM_DQM2

V1

MM_DQM3

V4