STM32H7B3II datasheet(13/238 Pages) STMICROELECTRONICS

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The flash memory is organized as follows:

•

Two independent 1 Mbyte banks of user flash memory, each one containing 128 user sectors of 8 Kbytes

each.

•

128 Kbytes of System flash memory from which the device can boot.

•

1 Kbyte of OTP (one-time programmable) memory containing option bytes for user configuration.

3.3.2

Secure access mode

In addition to other typical memory protection mechanism (RDP, PCROP), STM32H7B3xI devices embed the

Secure access mode, an enhanced security feature. This mode allows developing user-defined secure services

by ensuring, on the one hand code and data protection and on the other hand code safe execution.

Two types of secure services are available:

•

STMicroelectronics Root Secure Services:

These services are embedded in System memory. They provide a secure solution for firmware and third-party

modules installation. These services rely on cryptographic algorithms based on a device unique private key.

•

User-defined secure services:

These services are embedded in user flash memory. Examples of user secure services are proprietary user

firmware update solution, secure flash integrity check or any other sensitive applications that require a high level

of protection.

The secure firmware is embedded in specific user flash memory areas configured through option bytes.

Secure services are executed just after a reset and preempt all other applications to guarantee protected and safe

execution. Once executed, the corresponding code and data are no more accessible.

The above secure services are available only for Cortex®-M7 core operating in Secure access mode. The other

masters cannot access the option bytes involved in Secure access mode settings or the flash secured areas.

3.3.3

Embedded SRAM

All devices feature:

•

1 Mbyte of AXI-SRAM mapped onto AXI bus matrix in CPU domain (CD) split into:

–

AXI-SRAM1: 256 Kbytes

–

AXI-SRAM2: 384 Kbytes

–

AXI-SRAM3: 384 Kbytes

•

128 Kbytes of AHB-RAM mapped onto AHB bus matrix in CPU domain (CD) split into:

–

AHB-SRAM1: 64 Kbytes

–

AHB-SRAM2: 64 Kbytes

•

32 Kbytes of SRD-SRAM mapped in Smart Run Domain (SRD)

•

4 Kbytes of backup SRAM

The content of this area is protected against possible unwanted write accesses, and is retained in Standby or

VBAT mode.

•

RAM mapped to TCM interface (ITCM and DTCM):

Both ITCM and DTCM RAMs are 0 wait state memories that are accessible from the CPU or the MDMA (even in

Sleep mode) through a specific AHB slave of the CPU(AHBP).

•

64 Kbytes of ITCM-RAM (instruction RAM)

This RAM is connected to ITCM 64-bit interface designed for execution of critical real-times routines by the CPU.

•

128 Kbytes of DTCM-RAM (2x 64 Kbyte DTCM-RAMs on 2x32-bit DTCM ports)

The DTCM-RAM could be used for critical real-time data, such as interrupt service routines or stack/heap

memory. Both DTCM-RAMs can be used in parallel (for load/store operations) thanks to the Cortex®-M7 dual

issue capability.

STM32H7B3xI

Memories

DS13139 - Rev 8

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