STM32H7B3II datasheet(21/238 Pages) STMICROELECTRONICS

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Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt latency.

3.14

Extended interrupt and event controller (EXTI)

The EXTI controller performs interrupt and event management. In addition, it can wake up the processor, power

domains and/or SRD domain from Stop mode.

The EXTI handles up to 89 independent event/interrupt lines split into 28 configurable events and 61 direct

events.

Configurable events have dedicated pending flags, active edge selection, and software trigger capable.

Direct events provide interrupts or events from peripherals having a status flag.

3.15

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a programmable polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In

the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity. The CRC

calculation unit helps compute a signature of the software during runtime, to be compared with a reference

signature generated at link-time and stored at a given memory location.

3.16

Flexible memory controller (FMC)

The FMC controller main features are the following:

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Interface with static-memory mapped devices including:

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Static random access memory (SRAM)

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NOR flash memory/OneNAND flash memory

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PSRAM (4 memory banks)

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NAND flash memory with ECC hardware to check up to 8 Kbytes of data

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Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories

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8-,16-,32-bit data bus width

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Independent Chip Select control for each memory bank

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Independent configuration for each memory bank

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Write FIFO

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Read FIFO for SDRAM controller

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The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the FMC kernel clock

divided by 2.

3.17

Octo-SPI memory interface (OCTOSPI)

The OCTOSPI is a specialized communication interface targeting single, dual, quad or octal SPI memories.

The STM32H7B3xI embeds two separate Octo-SPI interfaces.

Each OCTOSPI instance supports single/dual/quad/octal SPI formats.

Multiplex of single/dual/quad/octal SPI over the same bus can be achieved using the integrated I/O manager.

The OCTOSPI can operate in any of the three following modes:

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Indirect mode: all the operations are performed using the OCTOSPI registers

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Status-polling mode: the external memory status register is periodically read and an interrupt can be

generated in case of flag setting

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Memory-mapped mode: the external memory is memory mapped and it is seen by the system as if it was an

internal memory supporting both read and write operations.

The OCTOSPI support two frame formats supported by most external serial memories such as serial PSRAMs,

serial NOR flash memories, Hyper RAMs and Hyper flash memories:

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The classical frame format with the command, address, alternate byte, dummy cycles and data phase

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The HyperBus™ frame format.

Multichip package (MCP) combining any of the above mentioned memory types can also be supported.

STM32H7B3xI

Extended interrupt and event controller (EXTI)

DS13139 - Rev 8

page 21/238

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