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STM32G0C1NET7XTR 数据表(PDF) 56 Page - STMicroelectronics

部件名 STM32G0C1NET7XTR
功能描述  Arm® Cortex®-M0 32-bit MCU, up to 512KB Flash, 144KB RAM,6x USART, timers, ADC, DAC, comm. I/Fs, AES, RNG, 1.7-3.6V
PDF  159 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32G0C1NET7XTR 数据表(HTML) 56 Page - STMicroelectronics

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30
30
45
45
C8
60
60
A4
78
98
C4
PB6
I/O
FT_fa
-
USART1_TX, TIM1_CH3, TIM16_CH1N,
FDCAN2_TX, SPI2_MISO/I2S2_MCK, LPTIM1_ETR,
I2C1_SCL, EVENTOUT, USART5_CTS, TIM4_CH1,
LPUART2_TX
COMP2_INP1
31
31
46
46
D7
61
61
A3
79
99
B3
PB7
I/O
FT_fa
-
USART1_RX, SPI2_MOSI/I2S2_SD, TIM17_CH1N,
USART4_CTS, LPTIM1_IN2, I2C1_SDA,
EVENTOUT, TIM4_CH2, LPUART2_RX
COMP2_INM7, PVD_IN
32
32
47
47 A12 62
62
B3
80
100
A1
PB8
I/O
FT_f
-
CEC, SPI2_SCK/I2S2_CK, TIM16_CH1,
FDCAN1_RX, USART3_TX, TIM15_BKIN,
I2C1_SCL, EVENTOUT, USART6_TX, TIM4_CH3
-
1
1
48
48
D9
63
63
C3
1
1
C3
PB9
I/O
FT_f
-
IR_OUT, UCPD2_FRSTX, TIM17_CH1,
FDCAN1_TX, USART3_RX, SPI2_NSS/I2S2_WS,
I2C1_SDA, EVENTOUT, USART6_RX, TIM4_CH4
-
1. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output
mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (for example to drive a LED).
2. After an RTC domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the RTC registers. The RTC registers are not reset
upon system reset. For details on how to manage these GPIOs, refer to the RTC domain and RTC register descriptions in the RM0444 reference manual.
3. Upon reset, a pull-down resistor might be present on PA8, PB15, PD0, or PD2 depending on voltage level on PA9,PA10, PD1, and PD3, respectively. In order to disable this
resistor, strobe the UCPDx_STROBE bit in SYSCFG_CFGR1 register during start-up sequence.
4. Pins PA9/PA10 can be remapped in place of pins PA11/PA12 (default mapping), using SYSCFG_CFGR1 register.
5. Upon reset, these pins are configured as SW debug alternate functions, and the internal pull-up on PA13 pin and the internal pull-down on PA14 pin are activated.
Table 12. Pin assignment and description (continued)
Pin number
Pin name
Alternate
functions
Additional
functions



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