7

Typical application

The STGAP2GS is design to drive Enhancement-mode GaN FETs, thanks to the separated turn-on and turn-off

output pins and to the optimized UVLO protection. Since the threshold voltage of GaN HEMTs is typically lower

than 2 V, attention must be paid to avoid induced turn on phenomena during high dV/dt transients. The most

common solution is to differentiate the values of turn-on and turn-off gate resistors, making the turn-off resistor

smaller than the turn-on one. In some cases, the use of negative driving might be needed (see Figure 6,

depending on the GaN characteristic and working conditions. In all cases the use of a 10 kΩ pull-down resistor

between the gate and Kelvin-Source pins is recommended, in order to avoid gate spikes while the driver is not yet

powered on.

Optimal driving of GaN switches requires an optimized routing of gate loop with minimized parasitic inductance;

in order to ease this task many GaN swithes comes with a dedicated Kelvin-Source pin dedicated for the gate

driving. Also the current loop of the and power stage and the connection to the power bulk capacitor should be

design with minimum loop inductance; some recommendations are provided in Section 8 .

Figure 5. Typical application diagram - Positive gate driving

GND_HS

VH_HS

VDD

MCU

HIN

LIN

VDD

VDD

C

R

C

R

C

R

C

R

GND_PWR

Load_ Phase

HV_BUS

VDD

GND

IN+

IN-

VH

GNDISO

VDD

GND

IN+

IN-

VH

GNDISO

I

S

O

L

A

T

I

O

N

Level

Shifter

Floating

Section

Control

Logic

Floating ground

UVLO

VH

GOFF

Control

Logic

UVLO

VDD

GON

I

S

O

L

A

T

I

O

N

Level

Shifter

Floating

Section

Control

Logic

Floating ground

UVLO

VH

GOFF

Control

Logic

UVLO

VDD

GON

GND_LS

VH_LS

Figure 6. Typical application diagram - Negative gate driving

VDD

MCU

HIN

LIN

VDD

VDD

C

R

C

R

C

R

C

R

VDD

GND

IN+

IN-

VH

VDD

GND

IN+

IN-

VH

GNDISO

I

S

O

L

A

T

I

O

N

Level

Shifter

Floating

Section

Control

Logic

Floating ground

UVLO

VH

GOFF

Control

Logic

UVLO

VDD

GON

I

S

O

L

A

T

I

O

N

Level

Shifter

Floating

Section

Control

Logic

Floating ground

UVLO

VH

GOFF

Control

Logic

UVLO

VDD

GON

GND_HS

VH_HS

VL_HS

+

VL

VH

+

GNDISO

GND_LS

VH_LS

VL_LS

+

VL

VH

+

GND_PWR

Load_ Phase

HV_BUS

STGAP2GS

Typical application

DS14152 - Rev 1

page 10/20