8

Layout

8.1

Layout guidelines and considerations

In order to optimize the PCB layout, the following considerations should be taken into account:

•

The power transistors must be placed as close as possible to the gate driver, so to minimize the gate

loop area and inductance that might cause noise, ringing and, in the worst cases, induced turn-on. Gate

loop inductance is crucial especially in GaN applications, where the VGSth is typically lower than other

technologies. To further minimize gate loop inductance, it is recommended to use an inner plane layer

to route the gate current return path (Kelvin-Source to GNDISO) flowing just underneath gate resistors.

Adequate vias to connect to the plane shall be placed near driver and power switch source pins.

•

When driving GaN switches the use of a 10 kΩ pull-down resistor between Gate and Kelvin-Source is also

recommended. Such resistor should be placed close to the GaN pins.

•

If the power transistor provides Kelvin-Source pin, it shall be used for gate driving while using the standard

source pin(s) only for load current. The standard source pin(s) and the Kelvin-Source pin shall not be

shorted together on PCB.

•

If the power transistor does not provide Kelvin-Source pin, the net connecting the driver (GNDISO pin) to

the power switch source pin shall use a dedicated trace/plane. The trace/plane shall start just on power

switch source pin to minimize path sharing between gate current and load current.

•

SMT ceramic capacitors (or different types of low-ESR and low-ESL capacitors) must be placed close to

each supply rail pins. A 100 nF capacitor must be placed between VDD and GND and between VH and

GNDISO, as close as possible to device pins, in order to filter high-frequency noise and spikes. In order to

provide local storage for pulsed current, a second capacitor with a value between 1 µF and 10 µF should

also be placed close to the supply pins.

•

It is good practice to add filtering capacitors close to logic inputs of the device (IN+, IN-), particularly for fast

switching or noisy applications.

•

To avoid degradation of the isolation between the primary and secondary side of the driver, there should

not be any trace or conductive area below the driver.

•

If the system has multiple layers, it is recommended to connect the VH and GNDISO pins to internal

ground or power planes through multiple vias of adequate size. These vias should be located close to

theIC pins to maximize thermal conductivity.

8.2

Layout example

An example of STGAP2GSN half-bridge suggested PCB layout with main signals highlighted by different colors

is shown in Figure 7. It is recommended to follow this example for correct positioning and connection of filtering

capacitors.

Figure 7. Half-bridge suggested PCB layout

Q1

Q2

U1

U2

CVH1

CVH2

CVDD1

ROFF

RON

G1

D1

S1

CIN

RIN

CVH1

CVH2

CVDD1

ROFF

RON

G2

D2

S2

CIN

RIN

TOP

BOTTOM

STGAP2GSN

Layout

DS14151 - Rev 1

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