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STGAP2HD 数据表(PDF) 4 Page - STMicroelectronics |
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STGAP2HD 数据表(HTML) 4 Page - STMicroelectronics |
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4 / 24 page ![]() 2 Pin description and connection diagram Figure 2. Pin connection (top view) 1 3 2 36 35 33 34 5 7 6 8 32 31 30 4 9 11 13 12 14 23 25 24 10 15 16 17 18 19 20 21 22 VDD INB INA iLOCK BRAKE SD N.C. N.C. GOFF_A VH_A GNDISO_A GON_A CLAMP_A N.C. N.C. GOFF_B VH_B GNDISO_B GON_B CLAMP_B GND N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. GNDISO_A N.C. Table 1. Pin description Pin number Pin name Type Function 6 VDD Power supply Control logic supply voltage. 7 INA Logic input Control logic input for Channel A, active high. 8 INB Logic input Control logic input for Channel B, active high. 9 SD Logic input Shutdown input, active low. 10 BRAKE Logic input Control logic input, active low. 11 iLOCK Analog input Interlocking enable/disable. 13 GND Power supply Control logic ground. 20 VH_B Power supply Channel B gate driving positive supply. 22 GON_B Analog output Channel B source output. 25 CLAMP_B Analog output Channel B Miller Clamp. 23 GOFF_B Analog output Channel B sink output. 24 GNDISO_B Power supply Channel B gate driving isolated ground. 30 VH_A Power supply Channel A gate driving positive supply. 31 GON_A Analog output Channel A source output. 33 CLAMP_A Analog output Channel A Miller Clamp. 32 GOFF_A Analog output Channel A sink output. 34, 35 GNDISO_A (1) Power supply Channel A gate driving isolated ground. 1, 2, 3, 4, 5, 12, 14, 15, 16, 17, 18 N.C. Not connected. 1. Both GNDISO_A pins must be connected and shorted together. STGAP2HD Pin description and connection diagram DS13652 - Rev 2 page 4/24 |
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