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©2020 Renesas Electronics Corporation

February 19, 2020

9SQL4952/9SQL4954/9SQL4958 Datasheet

Figure 5. Test Load for AC/DC Measurements

Figure 6. Test Setup for PCIe Clock Phase Jitter Measurements

Alternate Terminations

The device family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's

“Universal” Low-Power HCSL Outputs” for details.

Table 18. Terminations for AC/DC Measurements

Clock Source

Device Under Test (DUT)

Rs (Ω)

Zo (Ω)

L (cm)

CL (pF)

N/A

9SQL495x

Internal

85

12.7

2

Table 19. Terminations for PCIe Clock Phase Jitter Measurements

Clock Source

Device Under Test (DUT)

Rs (Ω)

Zo (Ω)

L (cm)

CL (pF)

N/A

9SQL495x

Internal

85

12.7

N/A

CK+

DUT

CK-

Zo (differential)

L

CL

CL

Test Points for

High Impedance

Probe

Oscillocope

(≥20GS/s)

SMA

Connectors

50

Coax

Cables

0.1uF

CKIN+

CK+

DUT

CKIN-

CK-

Zo (differential)

L

50