80C554 datasheet(2/76 Pages) PHILIPS

2 / 76 page

Philips Semiconductors

Preliminary specification

80C554/83C554/87C554

80C51 8-bit microcontroller – 6 clock operation

16K/512 OTP/ROM/ROMless, 7 channel 10 bit A/D, I2C, PWM,

capture/compare, high I/O, 64L LQFP

2000 Nov 10

DESCRIPTION

This data sheet describes the 6 clock version of the 8xC554. This

device is only available in 64L LQFP. The 8xC554 Single-Chip 8-Bit

Microcontroller is manufactured in an advanced CMOS process and

is a derivative of the 80C51 microcontroller family. The 87C554 has

the same instruction set as the 80C51. Three versions of the

derivative exist:

• 83C554—16k bytes ROM

• 80C554—ROMless version

• 87C554—16k bytes EPROM

The 87C554 contains a 16k

× 8 non-volatile EPROM, a 512 × 8

read/write data memory, five 8-bit I/O ports, one 8-bit input port, two

16-bit timer/event counters (identical to the timers of the 80C51), an

additional 16-bit timer coupled to capture and compare latches, a

15-source, four-priority-level, nested interrupt structure, an 7-input

ADC, a dual DAC pulse width modulated interface, two serial

interfaces (UART and I2C-bus), a “watchdog” timer and on-chip

oscillator and timing circuits. For systems that require extra

capability, the 8xC554 can be expanded using standard TTL

compatible memories and logic.

In addition, the 8xC554 has two software selectable modes of power

reduction—idle mode and power-down mode. The idle mode freezes

the CPU while allowing the RAM, timers, serial ports, and interrupt

system to continue functioning. Optionally, the ADC can be operated

in Idle mode. The power-down mode saves the RAM contents but

freezes the oscillator, causing all other chip functions to be

inoperative.

The device also functions as an arithmetic processor having

facilities for both binary and BCD arithmetic plus bit-handling

capabilities. The instruction set consists of over 100 instructions:

49 one-byte, 45 two-byte, and 17 three-byte. With an 8 MHz crystal,

58% of the instructions are executed in 0.75

µs and 40% in 1.5 µs.

Multiply and divide instructions require 3

µs.

FEATURES

• 80C51 central processing unit

• 16k × 8 EPROM expandable externally to 64k bytes

• An additional 16-bit timer/counter coupled to four capture registers

and three compare registers

• Two standard 16-bit timer/counters

• 512 × 8 RAM, expandable externally to 64k bytes

• Capable of producing eight synchronized, timed outputs

• A 10-bit ADC with seven multiplexed analog inputs

• Fast 8-bit ADC option – 9 µS at 16 MHz

• Two 8-bit resolution, pulse width modulation outputs

• Five 8-bit I/O ports plus one 8-bit input port shared with analog

inputs

• I2C-bus serial I/O port with byte oriented master and slave

functions

• On-chip watchdog timer

• Extended temperature ranges

• Full static operation – 0 to 16 MHz

• Operating voltage range: 2.7 V to 5.5 V (0 to 8 MHz) and

4.5 V to 5.5 V (8 to 16 MHz) commercial temperature

• Security bits:

– ROM – 2 bits

– OTP/EPROM – 3 bits

• 4 level priority interrupt

• 15 interrupt sources

• Full-duplex enhanced UART

– Framing error detection

– Automatic address recognition

• Power control modes

– Clock can be stopped and resumed

– Idle mode

– Power down mode

• Second DPTR register

• EMI reduction – 6 clock operation and ALE inhibit

• Programmable I/O pins

• Wake-up from power-down by external interrupts

• Software reset

• Power-on detect reset

• ADC charge pump disable

• ONCE mode

• ADC active in Idle mode

80C554 数据表(PDF) 2 Page - NXP Semiconductors

80C554 数据表(HTML) 2 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

数据表下载