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80C652 数据表(PDF) 13 Page - NXP Semiconductors |
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80C652 数据表(HTML) 13 Page - NXP Semiconductors |
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13 / 25 page  Phlips Semiconductors Product specification 80C652/83C652 CMOS single-chip 8-bit microcontrollers 1996 Aug 15 13 AC ELECTRICAL CHARACTERISTICS1, 2 (16 MHz type) 16MHz CLOCK VARIABLE CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 2 Oscillator frequency 1.2 16 MHz tLHLL 2 ALE pulse width 85 2tCLCL–40 ns tAVLL 2 Address valid to ALE low 8 tCLCL–55 ns tLLAX 2 Address hold after ALE low 28 tCLCL–35 ns tLLIV 2 ALE low to valid instruction in 150 4tCLCL–100 ns tLLPL 2 ALE low to PSEN low 23 tCLCL–40 ns tPLPH 2 PSEN pulse width 143 3tCLCL–45 ns tPLIV 2 PSEN low to valid instruction in 83 3tCLCL–105 ns tPXIX 2 Input instruction hold after PSEN 0 0 ns tPXIZ 2 Input instruction float after PSEN 38 tCLCL–25 ns tAVIV 2 Address to valid instruction in 208 5tCLCL–105 ns tPLAZ 2 PSEN low to address float 10 10 ns Data Memory tRLRH 3, 4 RD pulse width 275 6tCLCL–100 ns tWLWH 3, 4 WR pulse width 275 6tCLCL–100 ns tRLDV 3, 4 RD low to valid data in 148 5tCLCL–165 ns tRHDX 3, 4 Data hold after RD 0 0 ns tRHDZ 3, 4 Data float after RD 55 2tCLCL–70 ns tLLDV 3, 4 ALE low to valid data in 350 8tCLCL–150 ns tAVDV 3, 4 Address to valid data in 398 9tCLCL–165 ns tLLWL 3, 4 ALE low to RD or WR low 138 238 3tCLCL–50 3tCLCL+50 ns tAVWL 3, 4 Address valid to WR low or RD low 120 4tCLCL–130 ns tQVWX 3, 4 Data valid to WR transition 3 tCLCL–60 ns tDW 3, 4 Data setup time before WR 288 7tCLCL–150 ns tWHQX 3, 4 Data hold after WR 13 tCLCL–50 ns tRLAZ 3, 4 RD low to address float 0 0 ns tWHLH 3, 4 RD or WR high to ALE high 23 103 tCLCL–40 tCLCL+40 ns Shift Register tXLXL 5 Serial port clock cycle time3 0.75 12tCLCL µs tQVXH 5 Output data setup to clock rising edge3 492 10tCLCL–133 ns tXHQX 5 Output data hold after clock rising edge3 80 2tCLCL–117 ns tXHDX 5 Input data hold after clock rising edge3 0 0 ns tXHDV 5 Clock rising edge to input data valid3 492 10tCLCL–133 ns External Clock tCHCX 6 High time3 20 20 tCLCL – tCLCX ns tCLCX 6 Low time3 20 20 tCLCL – tCHCX ns tCLCH 6 Rise time3 20 20 ns tCHCL 6 Fall time3 20 20 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. These values are characterized but not 100% production tested. |
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