Data Sheet

LT4322

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Rev. 0

4 of 29

(TJ= -40°C to +150°C for the minimum and maximum values. TJA = 25°C for the typical values. VCATHODE = VVDDC =

VVDDA = 12V, VVSSA = VANODE= 0V unless otherwise noted.)

PARAMETER

SYMBOL

CONDITIONS/COMMENTS

MIN

TYP

MAX

UNITS

GATE Drive Output Low

Voltage

ΔVGATE(L)

CATHODE = 12V, IGATE = 1mA

5

50

mV

Propagation Delay,

CATHODE to GATE Rising

to 4V

tD,RISE

CATHODE = Step 1.5V to -0.2V,

CGATE= 10nF

550

1000

ns

CATHODE = Step 1.5V to -0.2V,

CGATE = 100nF

870

1500

GATE Rise Time, 1V to 4V

tRISE

CATHODE = Step 1.5V to -0.2V,

CGATE= 10nF

370

650

ns

CATHODE = Step 1.5V to -0.2V,

CGATE = 100nF

550

900

Propagation Delay,

CATHODE to GATE

Falling to 2V

tD,FALL

CATHODE = Step -0.1V to 0.1V,

CGATE = 10nF

130

260

ns

CATHODE = Step -0.1V to 0.1V,

CGATE = 100nF

330

660

GATE Fall Time, 9V to 2V

tFALL

CATHODE = Step -0.1V to 0.1V,

CGATE= 10nF

10

45

100

ns

CATHODE = Step -0.1V to 0.1V,

CGATE = 100nF

85

170

350

.

1

All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced

to VSSA unless otherwise specified. VSSA is the device ground and substrate.

2

The maximum VDDC to VSSA operating voltage is 60V. Users can add an external high-voltage depletion N-Channel

MOSFET to operate with input voltages above 60V. See the Operation at Voltages Above 60V section for more

details.

3

The minimum peak voltage of the VDDC input AC signal with respect to VSSA must ensure that the VDDA voltage

always exceeds 9V. The minimum VDDC peak voltage will depend upon application circuit architecture, parasitic

input inductance between the AC input supply and the VDDC pin, and VDDA hold-up capacitor value.

4

A DC supply voltage can be used to power the VDDA pin directly. In that case, the VDDC pin must be connected to

VSSA.