2

Pin configuration

Figure 2. Pin connection (top view)

ILim

En/Fault

dV/dt

GND

Vcc

Vcc

Source

Source

Vcc

Source

Source

Source

Source

Source

GND

dV

/dt

En /Fault

I

Lim

V

G

TSOT23-8L

DFN10 3x3

Table 1. Pin description

Pin #

Symbol

Function

TSOT23-8L

DFN10

1

4

ILim(1)

An RLim resistor between this pin and the Source pin sets the overload and

short-circuit current limit levels.

2

3

En/Fault

The En/Fault pin is a tri-state, bi-directional interface. During the normal

operation, the pin must be left floating, or it can be used to disable the

output of the device by pulling it to ground using an open drain or open

collector device.

If a thermal fault occurs, the voltage on this pin goes into an intermediate

state to signal a monitor circuit that the device is in thermal shutdown. It

can be connected to another device of this family to cause a simultaneous

shutdown during thermal events.

3

2

dV/dt

The internal dV/dt circuit controls the slew rate of the output voltage at

turn-on. The internal capacitor allows a ramp-up time of around 0.85 ms. An

external capacitor can be added to this pin to increase the ramp time. If an

additional capacitor is not required, this pin should be left open.

4

1

GND

Ground connection.

5-6

6-10

Source/VOUT

Connected to the source of the internal power MOSFET and to the output

terminal of the fuse.

-

5

VG

Gate driver output for the optional external reverse-blocking power MOS.

Leave floating if not used.

7-8

Exposed pad

VCC

Positive input voltage of the eFuse.

1. Important: missing or shorted RLim causes current limit circuit malfunction and may lead to device damage.

STEF12S

Pin configuration

DS13002 - Rev 5

page 3/31