7

Additional guidelines for SET mitigation

This section provides detailed design guidelines necessary to obtain the required performance against SET.

In this respect, we can identify two main areas for intervention: ground connection and external components

selection.

7.1

Ground connections

To achieve the best performance in terms of output voltage accuracy, noise immunity and robustness against

single event effects, it is recommended to implement a proper PCB layout by following the suggestions described

below.

According to qualitative simulations of single events, some very short SET (that is, a duration in the 100 ns

range) are strongly dependent on the stray inductances versus GND. The best solution to reduce the parasitic

inductance is the adoption of a GND plane (with separate power and sense paths where possible). By minimizing

the stray GND impedance, this approach is of great assistance in controlling the amplitude of the SET events

near the load.

If this solution is not applicable, we suggest using a star-bus topology, where the PCB reference GND connection

is close to the GND pin of the regulator.

To achieve a good GND sense, it is necessary to comply with the following rules:

•

connect the chip GND and the load one to a common point (used as star GND);

•

connect the power GND on the PCB to the star GND through an array of multiple vias;

•

for GND connectors/plugs: use separate plugs for power supply and testing probes;

•

connect I/O capacitors GND to the GND star by dedicated trace.

7.2

Capacitor selection

With reference to Figure 7. Heavy-ion test configuration for VOUT < 1.25 V, a combination of capacitors must be

present close to the I/O ports.

For the INPUT terminals, this may consist of a 150 μF bulk capacitor (CIN1), esr ~ 6 mΩ in parallel with a 100 nF

polyester one (CIN2). The latter is used for decoupling purposes.

For each of the two OUTPUT connections (pins 1, 2 and 6, 7) we suggest using a combination of a 150 μF bulk

capacitor with esr ~ 6 mΩ (COUT4, COUT5) in parallel with a polyester 100 nF one (COUT1, COUT2); the latter for

decoupling purposes.

These capacitors must be placed as close to the I/O terminals as possible with the bypass ones (CIn1, COUT1,2)

closer to the device to tackle stray PCB inductances related to the VIN/GND busses near to the device.

Regarding parts selection, we suggest the adoption of low-ESL, low ESR capacitors having characteristics similar

to those listed in Table 9. Still, for the bulk capacitors, using an array of paralleled capacitors works better than a

single component in limiting the intrinsic ESL (and thus against the short SETs).

RHFL6000L

Additional guidelines for SET mitigation

DS14125 - Rev 1

page 13/28