4

Integrated

Circuit

Systems, Inc.

ICS9DB401

1014B—09/07/06

The ICS9DB401 follows the Intel DB400 Differential Buffer Specification v2.0. This buffer provides four PCI-Express SRC

clocks. The ICS9DB401 is driven by a differential input pair from a CK409/CK410/CK410M main clock generator, such as the

ICS952601, ICS954101 or ICS954201. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew

(50ps) requirements.

General Description

Block Diagram

Power Groups

STOP

LOGIC

SRC_IN

SRC_IN#

DIF(3:0))

CONTROL

LOGIC

BYPASS#/PLL

SDATA

SCLK

PD

SPREAD

COMPATIBLE

PLL

4

IREF

OE(3:0)

4

M

U

X

Note: Polarities shown for OE_INV = 0.

VDD

GND

1

4

SRC_IN/SRC_IN#

5,11,18, 24

4

DIF(1,2,5,6)

N/A

27

IREF

28

27

Analog VDD & GND for PLL core

Description

Pin Number