DATASHEET

3.3 V 1:6 LVCMOS PLL Clock Generator

MPC9331

MPC9331 REVISION 7 March 11, 2016

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©2016 Integrated Device Technology, Inc.

The MPC9331 is a 3.3 V compatible, 1:6 PLL based clock generator targeted

for high performance low-skew clock distribution in mid-range to high-performance

telecom, networking, and computing applications. With output frequencies up to

240 MHz and output skews less than 150 ps, the device meets the needs of most

the demanding clock applications. The MPC9331 is specified for the temperature

range of 0°C to +70°C.

Features

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1:6 PLL Based Low-Voltage Clock Generator

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3.3 V Power Supply

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Generates Clock Signals up to 240 MHz

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Maximum Output Skew of 150 ps

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Differential LVPECL Reference Clock Input

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Alternative LVCMOS PLL Reference Clock Input

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Internal and External PLL Feedback

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Supports Zero-Delay Operation in External Feedback Mode

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PLL Multiplies the Reference Clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3

or x/4

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Synchronous Output Clock Stop in Logic Low Eliminates Output Runt Pulses

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Power_Down Feature Reduces Output Clock Frequency

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Drives Up to 12 Clock Lines

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32-Lead LQFP Packaging

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32-Lead Pb-Free Package Available

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Ambient Temperature Range 0°C to +70°C

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Internal Power-Up Reset

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Pin and Function Compatible to the MPC931

The MPC9331 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9331 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback

input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback

path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback

configuration and with the available post-PLL dividers (divide-by-2, divide-by-4, and divide-by-6), the internal VCO of the

MPC9331 is running at either 2x, 4x, 6x, 8x, or 12x of the reference clock frequency. In internal feedback configuration

(divide-by-8) the internal VCO is running 8x of the reference frequency. The frequency of the QA, QB, QC output banks is a

division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB, and FSELC

pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4.

The REF_SEL pin selects the differential LVPECL or the LVCMOS compatible input as the reference clock signal. The PLL_EN

control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is

routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency

specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) by deasserting the

OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to

missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling

the PLL to recover to normal operation. The MPC9331 output clock stop control allows the outputs to start and stop

synchronously in logic low state, without the potential generation of runt pulses.

The MPC9331 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept

LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50

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transmission lines. For series terminated transmission lines, each of the MPC9331 outputs can drive one or two traces giving the

devices an effective fanout of 1:12. The device is packaged in a 7x7 mm2 32-lead LQFP package.

MPC9331

LOW VOLTAGE

3.3 V LVCMOS 1:6

CLOCK GENERATOR

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-03

AC SUFFIX

32-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 873A-03

PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016