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MPC9331 数据表(PDF) 2 Page - Renesas Technology Corp |
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MPC9331 数据表(HTML) 2 Page - Renesas Technology Corp |
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2 / 14 page ![]() MPC9331 REVISION 7 March 11, 2016 2 ©2016 Integrated Device Technology, Inc. MPC9331 Data Sheet 3.3 V 1:6 LVCMOS PLL CLOCK GENERATOR Figure 1. MPC9331 Logic Diagram OE/MR Bank A PLL 1 0 2 4 6 1 0 0 1 8 1 0 1 0 1 2 1 0 1 0 3 QA0 QA1 QB0 QB1 QC0 QC1 Bank B Bank C 25k 25k 3 x 25 K 25k VCC VCC 25k VCC 25k VCC 3 x 25 K VCC CLK Stop CLK Stop CLK Stop Ref FB VCO CLK_STOP1 CLK_STOP0 FSELC FSELB FSELA PLL_EN PWR_DN FB_SEL FB_IN REF_SEL CCLK PCLK PCLK 3 x 25 K 200 – 480 MHz Power_On Reset |
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