ISL81601 datasheet(39/54 Pages) RENESAS

39 / 54 page

FN9299 Rev.3.1

Page 39 of 53

May 27, 2021

ISL81601

5. Functional Description

Figure 53. Frequency Dithering Operation

The dither frequency FDITHER can be calculated by Equation 15. Renesas recommends setting CDITHER between

10nF and 1µF. With a too low CDITHER the part may not be able to set to Dither mode. With a higher CDITHER, the

discharge power loss at disable or power off is higher, leading to a higher thermal stress to the internal discharge

circuit.

5.12

Parallel Operation Current Sharing

Multiple ISL81601 controlled buck-boost DC/DC converters can be paralleled to each other in cascade as

described in “Frequency Synchronization and Dithering” on page 38. The currents in the paralleled converters can

be shared by feeding the same connected COMP pin voltage signal to the reference of the current control loops in

each IC. However, the current sharing accuracy is not ideal due to the loose tolerance in RAMP and current sense

circuit settings. To achieve an acceptable current sharing accuracy, an external active current sharing circuit is

recommended, as shown in Figure 54 on page 40.

CLKOUT/

DITHER

CDITHER

ISL81601

FDITHER

2.2V

1.05V

a. Frequency Dithering Operation

b. CLKOUT/DITHER Pin Voltage Waveform in Dither Operation

FDITHER

3.865x10e 6

–



CDITHER

-----------------------------------------

(EQ. 15)

ISL81601 数据表(PDF) 39 Page - Renesas Technology Corp