OXCF950 datasheet(39/66 Pages) OXFORD

39 / 66 page

Page 39

OXCF950 rev B DATA SHEET V 1.0

OXFORD SEMICONDUCTOR LTD.

6.6

Interrupts & Sleep Mode

The serial interrupt on the OXCF950 is routed through to

the OXCF950 interrupt control, regardless of MCR[3].

6.6.1

Interrupt Enable Register ‘IER’

Serial channel interrupts are enabled using the Interrupt

Enable Register (‘IER’).

IER[0]: Receiver data available interrupt mask

logic 0 ⇒Disable the receiver ready interrupt.

logic 1 ⇒Enable the receiver ready interrupt.

IER[1]: Transmitter empty interrupt mask

logic 0 ⇒Disable the transmitter empty interrupt.

logic 1 ⇒Enable the transmitter empty interrupt.

IER[2]: Receiver status interrupt

Normal mode:

logic 0 ⇒ Disable the receiver status interrupt.

logic 1 ⇒ Enable the receiver status interrupt.

9-bit data mode:

logic 0 ⇒ Disable receiver status and address bit

interrupt.

logic 1 ⇒

Enable receiver status and address bit

interrupt.

In 9-bit mode (i.e. when NMR[0] is set) reception of a

character with the address-bit (9th bit) set can generate a

level 1 interrupt if IER[2] is set.

IER[3]: Modem status interrupt mask

logic 0 ⇒ Disable the modem status interrupt.

logic 1 ⇒ Enable the modem status interrupt.

IER[4]: Sleep mode

logic 0 ⇒ Disable sleep mode.

logic 1 ⇒ Enable sleep mode whereby the internal clock

of the channel is switched off.

Sleep mode is described in section 6.6.4.

IER[5]: Special character interrupt mask or alternate

sleep mode

9-bit data framing mode:

logic 0 ⇒ Disable the special character receive interrupt.

logic 1 ⇒ Enable the special character receive interrupt.

In 9-bit data mode, The receiver can detect up to four

special characters programmed in Special Character 1 to

4. When IER[5] is set, a level 5 interrupt is asserted when a

match is detected.

650/950 modes (non-9-bit data framing):

logic 0 ⇒ Disable the special character receive interrupt.

logic 1 ⇒ Enable the special character receive interrupt.

In 16C650 compatible mode when the device is in

Enhanced mode (EFR[4]=1), this bit enables the detection

of special characters. It enables both the detection of

XOFF characters (when in-band flow control is enabled via

EFR[3:0]) and the detection of the XOFF2 special

character (when enabled via EFR[5]).

750 mode (non-9-bit data framing):

logic 0 ⇒ Disable alternate sleep mode.

logic 1 ⇒ Enable alternate sleep mode whereby the

internal clock of the channel is switched off.

In 16C750 compatible mode (i.e. non-Enhanced mode),

this bit is used an alternate sleep mode and has the same

effect as IER[4]. (See section 6.6.4)

IER[6]: RTS interrupt mask

logic 0 ⇒ Disable the RTS interrupt.

logic 1 ⇒ Enable the RTS interrupt.

This enable is only operative in Enhanced mode

(EFR[4]=1). In non-Enhanced mode, RTS interrupt is

permanently enabled.

IER[7]: CTS interrupt mask

logic 0 ⇒ Disable the CTS interrupt.

logic 1 ⇒ Enable the CTS interrupt.

This enable is only operative in Enhanced mode

(EFR[4]=1). In non-Enhanced mode, CTS interrupt is

permanently enabled.

OXCF950 数据表(PDF) 39 Page - Oxford Semiconductor

OXCF950 数据表(HTML) 39 Page - Oxford Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

数据表下载