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ADG2108BCPZ-R2 数据表(PDF) 8 Page - Analog Devices

部件名 ADG2108BCPZ-R2
功能描述  I2C CMOS 8 횞 10 Unbuffered Analog Switch Array with Dual/Single Supplies
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADG2108BCPZ-R2 数据表(HTML) 8 Page - Analog Devices

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ADG2108
Rev. 0 | Page 8 of 28
ADG2108 Limit at TMIN, TMAX
Parameter1
Conditions
Min
Max
Unit
Description
t11
Standard mode
1000
ns
tRCL, rise time of SCL signal
Fast mode
20 + 0.1 CB
300
ns
High speed mode2
CB = 100 pF maximum
10
40
ns
CB = 400 pF maximum
20
80
ns
t11A
Standard mode
1000
ns
tRCL1, rise time of SCL signal after a repeated start
Fast mode
20 + 0.1 CB
300
ns
condition and after an acknowledge bit
High speed mode2
CB = 100 pF maximum
10
80
ns
CB = 400 pF maximum
20
160
ns
t12
Standard mode
300
ns
tFCL, fall time of SCL signal
Fast mode
20 + 0.1 CB
300
ns
High speed mode2
CB = 100 pF maximum
10
40
ns
CB = 400 pF maximum
20
80
ns
tSP
Fast mode
0
50
ns
Pulse width of suppressed spike
High speed mode2
0
10
ns
1 Guaranteed by initial characterization. All values measured with input filtering enabled. CB refers to capacitive load on the bus line; tR and tF are measured between
0.3 VDD and 0.7 VDD.
2 High speed I2C is available only in -HS models.
3 A device must provide a data hold time for SDA to bridge the undefined region of the SCL falling edge.
TIMING DIAGRAM
P
S
S
P
SDA
SCL
S = START CONDITION
P = STOP CONDITION
t7
t6
t4
t2
t11
t12
t1
t3
t5
t6
t10
t8
t9
Figure 2. Timing Diagram for 2-Wire Serial Interface



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