LT8650SPJVPBF datasheet(22/34 Pages) AD

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LT8650SP

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

Figure 5. SS Pin Tracking

Output Voltage Tracking and Soft-Start

TheLT8650SPallowstheusertoprogramitsoutputvoltage

ramp rate with the SS pin. An internal 2μA current pulls

up the SS pin to VCC. Putting an external capacitor on SS

enables soft starting the output to prevent current surge

on the input supply. During the soft-start ramp the output

voltage will proportionally track the SS pin voltage. For

output tracking applications, SS can be externally driven

by another voltage source. From 0V to 0.04V, the SS pin

will stop the corresponding channel from switching, thus

allowing the SS pin to be used as a shutdown pin. From

0.04V to 0.8V, the SS voltage will override the internal

0.8V reference input to the error amplifier, thus regulating

the FB pin voltage to that of SS pin (Figure 5). When SS is

above 0.8V, tracking is disabled and the feedback voltage

will regulate to the internal reference voltage. The SS pin

may be left floating if the function is not needed. Note that

in both Burst Mode and forced continuous mode (FCM)

the LT8650SP will not discharge the output to regulate

to a lower SS voltage. This is achieved by disabling FCM

when the SS voltage is below 2V.

In Burst Mode operation (SYNC low), an active pull-down

circuit is connected to the SS pin which will discharge the

external soft-start capacitor in the case of fault conditions

and restart the ramp when the faults are cleared. Fault

conditions that clear the soft-start capacitor are the cor-

responding EN/UV pin below 0.74V, VIN1 voltage falling

too low, or thermal shutdown.

Output Power Good

When the LT8650SP’s output voltage is within the ±7.5%

window of the regulation point, which is a FB voltage in

the range of 0.74V to 0.86V (typical), the output voltage

is considered good and the open-drain PG pin goes high

impedance and is typically pulled high with an external

resistor. Otherwise, the internal pull-down device will pull

the PG pin low. To prevent glitching both the upper and

lower thresholds include 0.3% of hysteresis.

The PG pin is also actively pulled low during several fault

conditions: corresponding EN/UV pin below 0.74V, VCC

voltage falling too low, VIN1 under voltage, or thermal

shutdown.

Sequencing

Startup sequencing and tracking can be configured in sev-

eral ways with the LT8650SP. One channel can be required

to be valid before enabling the other channel to sequence

their startup order. This can be done by connecting the

PG pin of the first channel to either the EN/UV pin or SS

pin of the second channel. The SS pin of the first channel

can also be connected to the EN/UV pin of the second

channel (see Figure 6).

The channels can also be started at the same time where

the output voltages can track in a ratiometric fashion (see

Figure 6).

Paralleling

To increase the possible output current the two channels

can be connected in parallel to the same output. To do this

the VC, SS, and FB pins of each channel are connected

together, while each channel’s SW node is connected to

the common output through its own inductor. External

compensation network must be used when paralleling

outputs. Figure 7 shows an application where the two

channels of one LT8650SP regulator are combined to get

one output capable of 12A DC with 16A peak transients.

SS VOLTAGE (V)

0.2

0.4

0.6

0.8

1.0

1.2

0.2

0.4

0.6

0.8

1.0

8650sp F05

LT8650SPJVPBF 数据表(PDF) 22 Page - Analog Devices

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