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CS4811 数据表(PDF) 1 Page - Applied Micro Circuits Corporation

部件名 CS4811
功能描述  Multi Protocol Termination for 2047 Channels
PDF  5 Pages
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制造商  AMCC [Applied Micro Circuits Corporation]
网页  http://www.amcc.com
标志 AMCC - Applied Micro Circuits Corporation

CS4811 数据表(HTML) 1 Page - Applied Micro Circuits Corporation

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Empowering Intelligent Optical Networks
FINAL Product Brief
TIGRIS
OC-48 Multi Protocol Termination for 2047 Channels
Part Number S4811, Rev. 2.4 July 2006
FINAL Information - The information contained in this document is
about a product that has been fully tested, characterized, and is produc-
tion released. All features described herein are supported. Contact
AMCC for updates to this document and the latest product status.
FINAL Product Brief
TIGRIS
OC-48 Multi Protocol Termination for 2047 Channels
Part Number S4811, Rev. 2.4 July 2006
Data services and performance monitoring
• Store and forward architecture with extensive buffering using
external DDR SDRAM.
• 2047 bi-directional ATM/HDLC channels that can be
assigned to tributaries from STS-12 to DS0.
• Bit Synchronous HDLC support all channels (DS3 and lower
rate)
• Byte synchronous HDLC support for all channels (STS-1 and
higher rate)
• Direct Map ATM support.
• G.832 E3 ATM support.
• Support for up to 48 DS3 PLCP ATM mapped channels.
• Support for up to 48 Sub-Rate DS3 channels.
FTI-2 line interface
• Four independent STS-12 capable interfaces selectable from
four serial 622 MHz LVDS Flexible Tributary interfaces (FTI-
2) or one Parallel FTI 8-bit x 78MHz Interface. Parallel
Interface is compatible with standard Telecom Bus interfaces.
• An Expansion mode allows multiple TIGRIS devices to share
a single FTI interface (allows up to 8K channels).
• Glueless interface to up to four AMCC Evros framers.
System Interface
• SPI-3 32bit @ 104MHz for cells/packets and error status.
• The SPI-3 supports four interleaved channels (four logical
PHY ports).
• Pre-pended packet tag for channel ID, length, error status,
TX queue priority, and TX per packet loopback.
Device Specifications
• 899 PBGA (31x31mm with 1mm ball pitch) package
• 1.2V core, 2.5V I/O
• Estimated 3W power consumption
TIGRIS is a high density data-termination device supporting 2047 channels operating at an aggregate rate of 2.488Gbps. The
device aggregates and terminates both ATM cells and HDLC frames, enabling ATM services such as Cell Relay, IMA, AAL2/5, and
frame based services, such as PPP, Frame Relay, and Multi-link PPP and Multi-link Frame Relay. The 2047 individually assignable
channels can be configured for Frame Relay, HDLC, PPP, and or ATM services for DS0, NxDS0, DS1/E1, DS3/E3, STS-1c, STS-3c
and STS-12c rates.
TIGRIS supports up to 48 channels of subrate DS3 services interoperating with major CSU/DSU vendors protocols and can be com-
bined with AMCC’s nP3700 to provide AAL2/5, IMA, and Multilink services for all 2047 channels.
Figure 1: Block Diagram
MICROPROCESSOR I/F
QUEUE MANAGER
MEMORY
MANAGER
EXTERNAL
SDRAM
(RX Frame storage)
JTAG PORT
HDLC / ATM
Processor
RECEIVE
FIFO
TRANSMIT
FIFO
TRANSMIT
4X FTI
FRAMER
RECEIVE
4X FTI
FRAMER
TSX
TSOP
TPRTY
TMOD[1:0]
TERR
TEOP
TENB
TFCLK
STPA
PTPA
DTPA[3:0]
TADR[1:0]
RDAT[0:31]
RSX
RSOP
RPRTY
RMOD[1:0]
RERR
REOP
RENB
RVAL
EXTERNAL MEMORY I/F
SUBRATE
DS3
/ DS3
PLCP
FRAMER
ATI SERIAL CLK and
DATA I/F
12
24
EXTERNAL
SDRAM
(TX Frame storage)
RFCLK
TDAT[0:31]
RSA[3:0]
PMON
SERIAL
ATI
INTERFACES
SCLK
PARALLEL 8 BIT @77Mhz
INTERFACE
4 x 622Mhz LVDS
SERIAL INTERFACES
LTX_DATA[7:0]]
LTX_CONTROL_SIGNALS
LRX_DATA[7:0]]
LRX_CONTROL_SIGNALS
LRX_DATA622[3:0]
LRX_CLK622[3:0]
LRX_CONTROL622[3:0]
LTX_DATA622[3:0]
LTX_CLK622[3:0]
LTX_CONTROL622[3:0]
Data services and performance monitoring
• Store and forward architecture with extensive buffering using
external DDR SDRAM.
• 2047 bi-directional ATM/HDLC channels that can be
assigned to tributaries from STS-12 to DS0.
• Bit Synchronous HDLC support all channels (DS3 and lower
rate)
• Byte synchronous HDLC support for all channels (STS-1 and
higher rate)
• Direct Map ATM support.
• G.832 E3 ATM support.
• Support for up to 48 DS3 PLCP ATM mapped channels.
• Support for up to 48 Sub-Rate DS3 channels.
FTI-2 line interface
• Four independent STS-12 capable interfaces selectable from
four serial 622 MHz LVDS Flexible Tributary interfaces (FTI-
2) or one Parallel FTI 8-bit x 78MHz Interface. Parallel
Interface is compatible with standard Telecom Bus interfaces.
• An Expansion mode allows multiple TIGRIS devices to share
a single FTI interface (allows up to 8K channels).
• Glueless interface to up to four AMCC Evros framers.
System Interface
• SPI-3 32bit @ 104MHz for cells/packets and error status.
• The SPI-3 supports four interleaved channels (four logical
PHY ports).
• Pre-pended packet tag for channel ID, length, error status,
TX queue priority, and TX per packet loopback.
Device Specifications
• 899 PBGA (31x31mm with 1mm ball pitch) package
• 1.2V core, 2.5V I/O
• Estimated 3W power consumption
Data Services and Performance Monitoring
• Store and forward architecture with extensive buffering using
external DDR SDRAM.
• 2047 bi-directional ATM/HDLC channels that can be
assigned to tributaries from STS-12 to DS0.
• Bit synchronous HDLC support all channels (DS3 and lower
rate).
• Byte synchronous HDLC support for all channels (STS-1 and
higher rate).
• Direct Map ATM support.
• G.832 E3 ATM support.
• Support for up to 48 DS3 PLCP ATM mapped channels.
• Support for up to 48 sub-rate DS3 channels.
FTI-2 Line Interface
• Four independent STS-12 capable interfaces selectable from
four serial 622 MHz LVDS Flexible Tributary interfaces (FTI-
2) or one Parallel FTI 8-bit x 78MHz Interface. Parallel
Interface is compatible with standard Telecom Bus interfaces.
• An expansion mode allows multiple TIGRIS devices to share
a single FTI interface (allows up to 8K channels).
• Glueless interface to up to four AMCC Evros framers.
System Interface
• SPI-3 32bit @ 104MHz for cells/packets and error status.
• The SPI-3 supports four interleaved channels (four logical
PHY ports).
• Pre-pended packet tag for channel ID, length, error status,
TX queue priority, and TX per packet loopback.
Device Specifications
• 899 PBGA (31x31mm with 1mm ball pitch) package with
Green/RoHS compliant option
• 1.2V core, 2.5V I/O
• 6.0W maximum power consumption


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