ICS9DB803D

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2

IDT®

EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2

21

ICS9DB803D

REV N 071013

Revision History

Rev.

Issue Date

Issuer

Description

Page #

A

8/15/2006

Updated electrical characteristics for final data sheet

-

B

Added Input Clock Specs

C

2/29/2008

Updated Input Clock Specs

D

3/18/2008

Fixed typo in Input Clock Parameters

E

3/28/2008

Updated Electrical Char tables

F

4/10/2008

Updated Input Clock Specs

G

1/13/2009

Corrected part ordering information

H

10/7/2009

1. Clarified that Vih and Vil values were for Single ended inputs

2. Added Differential Clock input parameters.

3. Updated Electrical Characteristics to add propagation delay and

phase noise information.

4. Added SMBus electrical characteristics

5. Added foot note about DIF input running in order for the SMBus

interface to work

6. Added foot note to Byte 1 about functionality of OE bits and OE

pins.

7. Updated/Reformatted General Description

Various

J

1/27/2011

Updated Termination Figure 4

12

K

5/9/2011

1. Update pin 2 pin-name and pin description from VDD to VDDR. This

highlights that optimal peformance is obtained by treating VDDR as in

analog pin. This is a document update only, there is no silicon change.

Various

L

8/27/2012

Updated Vswing conditions to include "single-ended measurement"

7

M

9/18/2012

Updated Byte 2, bits 0~7 per char review. Outputs can be programmed

with Byte 2 to be Stoppable or Free-Run with DIF_Stop pin, not the OE

pins.

14

N

7/10/2013

R. Wei

Typo discovered on front page "Output Features" section. Was: “50 –

110MHz operation in PLL mode”; changed to: "50 – 100MHz operation

in PLL mode”

1