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ICS9LPR502 数据表(PDF) 21 Page - Renesas Technology Corp |
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ICS9LPR502 数据表(HTML) 21 Page - Renesas Technology Corp |
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21 / 30 page  IDTTM/ICSTM 56-pin CK505 w/Fully Integrated Voltage Regulator 1124D—02/26/09 Advance Information ICS9LPR502 56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR 21 Datasheet Byte 5 Clock Request Enable/Configuration Register Bit Pin Name Description Type Default 7 CR#_A_EN Enable CR#_A (clk req), PCI0_OE must be = 1 for this bit to take effect RW 0 6 CR#_A_SEL Sets CR#_A to control either SRC0 or SRC2 RW 0 5 CR#_B_EN Enable CR#_B (clk req) RW 0 4 CR#_B_SEL Sets CR#_B -> SRC1 or SRC4 RW 0 3 CR#_C_EN Enable CR#_C (clk req) RW 0 2 CR#_C_SEL Sets CR#_C -> SRC0 or SRC2 RW 0 1 CR#_D_EN Enable CR#_D (clk req) RW 0 0 CR#_D_SEL Sets CR#_D -> SRC1 or SRC4 RW 0 Byte 6 Clock Request Enable/Configuration and Stop Control Register Bit Pin Name Description Type Default 7 CR#_E_EN Enable CR#_E (clk req) -> SRC6 RW 0 6CR#_F_EN Enable CR#_F (clk req) -> SRC8 RW 0 5 CR#_G_EN Enable CR#_G (clk req) -> SRC9 RW 0 4 CR#_H_EN Enable CR#_H (clk req) -> SRC10 RW 0 3 Reserved Reserved RW 0 2 Reserved Reserved RW 0 1 SSCD_STP_CRTL (SRC1) If set, SSCD (SRC1) stops with PCI_STOP# RW 0 0 SRC_STP_CRTL If set, SRCs (except SRC1) stop with PCI_STOP# RW 0 Byte 7 Vendor ID/ Revision ID Bit Pin Name Description Type Default 7 Rev Code Bit 3 R X 6 Rev Code Bit 2 R X 5 Rev Code Bit 1 R X 4 Rev Code Bit 0 R X 3 Vendor ID bit 3 R 0 2 Vendor ID bit 2 R 0 1 Vendor ID bit 1 R 0 0 Vendor ID bit 0 R 1 Byte 8 Device ID and Output Enable Register Bit Pin Name Description Type Default 7 Device_ID3 R 0 6 Device_ID2 R 0 5 Device_ID1 R 0 4 Device_ID0 R 0 3 Reserved Reserved RW 0 2 Reserved Reserved RW 0 1 SE1_OE Output enable for SE1 RW 0 0 SE2_OE Output enable for SE2 RW 0 Byte 9 Output Control Register Bit Pin Name Description Type Default 7 PCIF5 STOP EN Allows control of PCIF5 with assertion of PCI_STOP# RW 0 6 TME_Readback Truested Mode Enable (TME) strap status R 0 5 Reserved Reserved RW 1 4 Test Mode Select Allows test select, ignores REF/FSC/TestSel RW 0 3 Test Mode Entry Allows entry into test mode, ignores FSB/TestMode RW 0 2 IO_VOUT2 IO Output Voltage Select (Most Significant Bit) RW 1 1 IO_VOUT1 IO Output Voltage Select RW 0 0 IO_VOUT0 IO Output Voltage Select (Least Significant Bit) RW 1 01 See Table 3: V_IO Selection (Default is 0.8V) Test mode Free running normal operation Outputs HI-Z - Stops with PCI_STOP# assertion no overclocking - Outputs = REF/N Enable CR#_E 1 01 Enable CR#_H Enable CR#_G Enable CR#_F Stops with PCI_STOP# assertion Free Running Stops with PCI_STOP# assertion Disable CR#_H Free Running 0 Disable CR#_E Disable CR#_F Disable CR#_G Disable CR#_D CR#_D -> SRC1 Enable CR#_A CR#_A -> SRC2 Enable CR#_B CR#_B -> SRC4 Enable CR#_C CR#_C -> SRC2 Enable CR#_D CR#_D -> SRC4 Disable CR#_B CR#_B -> SRC1 Disable CR#_C CR#_C -> SRC0 Disable CR#_A CR#_A -> SRC0 01 Table of Device identifier codes, used for differentiating between CK505 package options, etc. See Device ID Table - - Disabled - - Revision ID Vendor specific 01 Vendor ID ICS is 0001, binary Enabled Enabled Normal operation Disabled |
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